Method of Fabricating High Efficiency CIGS Solar Cells

ABSTRACT

A method is disclosed for fabricating high efficiency CIGS solar cells including the deposition of a multi-component metal precursor film on a substrate. The substrate is then inserted into a system suitable for exposing the precursor to a chalcogen to form a chalcogenide TFPV absorber. One or more Na precursors are used to deposit a Na-containing layer on the precursor film in the system. This method eliminates the use of dedicated equipment and processes for introducing Na to the TFPV absorber.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. Provisional Patent ApplicationSer. No. 61/701,290, filed on Sep. 14, 2012, which is hereinincorporated by reference for all purposes.

FIELD OF THE DISCLOSURE

This disclosure relates to thin film photovoltaic devices, and moreparticularly, to an absorber layer for a thin film photovoltaic devicethat has a graded bandgap, and methods of forming the same. Morespecifically, methods of developing absorbers for copper indium gallium(sulfide) selenide (CIG(S)Se, or CIGS) solar cells are discussed.

BACKGROUND OF THE DISCLOSURE

Solar cells are photovoltaic (PV) devices that convert light intoelectrical energy. Solar cells have been developed as clean, renewableenergy sources to meet growing demand. Solar cells have been implementedin a wide number of commercial markets including residential rooftops,commercial rooftops, utility-scale PV projects, building integrated PV(BIPV), building applied PV (BAPV), PV in electronic devices, PV inclothing, etc. Currently, crystalline silicon solar cells (bothmono-crystalline and multi-crystalline) are the dominant technologies inthe market. Crystalline silicon (cSi) solar cells must use a thicksubstrate (>100 um) of silicon to absorb the sunlight since it has anindirect bandgap and low absorption coefficient. The use of a thicksubstrate also means that the crystalline silicon solar cells must usehigh quality material to provide long carrier lifetimes. Therefore,crystalline silicon solar cell technologies lead to increased costs.Thin film photovoltaic (TFPV) solar devices based on amorphous silicon(a-Si), CIGS, cadmium telluride (CdTe), copper zinc tin sulfide (CZTS),etc. provide an opportunity to increase the material utilization sinceonly thin films (<10 um) are generally required. The thin film solarcells may be formed from amorphous, nanocrystalline, micromorph,micro-crystalline, polycrystalline, or mono-crystalline materials. TFPVdevices may include a single absorber layer for converting light intoelectricity, or multiple absorber layers with tuned absorption spectrafor converting light into electricity in a tandem configuration. Thetandem configuration might be a two-terminal device, or a multi-terminal(e.g. four-terminal) device structure. The multi-terminal devicestructure might be comprised of one stack of layers on one substrate, orinvolve different stacks of layers on multiple stacked substrates.

TFPV devices provide an opportunity to reduce energy payback time, andreduce water usage for solar panel manufacturing. Typical CdTe and CZTSfilms have bandgaps of about 1.5 eV and therefore, are an ideal matchfor the AM1.5G solar spectrum to allow for high efficiencies. Theabsorption coefficient for CdTe is about 10⁵/cm and the absorptioncoefficient for CZTS is about 10⁴/cm. CIGS films have bandgaps in therange of 1.0 eV (CIS) to 1.65 eV (CGS) and are also efficient absorbersacross the entire solar spectrum. The absorption coefficient for CIGS isalso about 10⁵/cm. Among the thin film solar technologies, CIGS hasdemonstrated the best lab cell efficiency (over 20%) and the best largearea module efficiency (>15%).

A class of PV absorber films of special interest is formed as CIGS-typeIB-IIIA-VIA multinary chalcogenide compounds from Groups IB, IIIA, andVIA of the periodic table. Group IB includes Cu, Ag, and Au. Group IIIAincludes B, Al, Ga, In, and TI. Group VIA includes O, S, Se, Te, and Po.Additionally, the IB-IIIA-VIA materials can be doped with dopants fromGroups VIII, IIB, IVA, VA, and VIIA of the periodic table. Group VIIIincludes Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, and Pt. Group IIB includes Zn,Cd, and Hg. Group IVA includes C, Si, Ge, Sn, and Pb. Group VA includesN, P, As, Sb, and Bi. Group VIIA includes F, CI, Br, I, and At. Otherpotential absorber materials of interest include kesterites like CZTS,cuprous oxide, iron sulfide, tungsten sulfide, calcium nitride, zincphosphide, barium silicide, etc.

TFPV devices can be fabricated at the cell level or the panel level,thus further decreasing the manufacturing costs. As used herein, thecell level is understood to mean an individual unit that can be combinedwith other units to form a module. The cells may be rigid or flexible.As used herein, the panel level is understood to mean a large TFPVstructure that is not composed of smaller units. Generally, the panelsare similar in size to the aforementioned modules. For economy oflanguage, the phrase “TFPV device” will be understood to refer to eithera solar cell or a panel without distinction. Furthermore, TFPV devicesmay be fabricated on inexpensive substrates such as glass, plastics, andthin sheets of metal. Examples of suitable substrates comprise floatglass, low-iron glass, borosilicate glass, flexible glass, flexibleceramics, specialty glass for high temperature processing, stainlesssteel, carbon steel, aluminum, cladded foils, copper, polyimide,plastics, etc. Furthermore, the substrates may be processed in manyconfigurations such as single substrate processing, multiple substratebatch processing, in-line continuous processing, roll-to-rollprocessing, etc.

The increasing demand for environmentally friendly, sustainable andrenewable energy sources is driving the development of large area, thinfilm photovoltaic devices. With a long-term goal of providing asignificant percentage of global energy demand, there is a concomitantneed for Earth-abundant, high conversion efficiency materials for use inphotovoltaic devices. A number of Earth abundant, direct-bandgapsemiconductor materials now seem to show evidence of the potential forboth high efficiency and low cost in Very Large Scale (VLS) production(e.g. greater than 100 gigawatt (GW)), yet their development andcharacterization remains difficult because of the complexity of thematerials systems involved.

Among the TFPV technologies, CIGS and CdTe are the two that have reachedvolume production with greater than 11% stabilized module efficiencies.However, the supply of In, Ga and Te may impact annual production ofCIGS and CdTe solar panels. Moreover, price increases and supplyconstraints in Ga and In could result from the aggregate demand forthese materials used in flat panel displays (FPD) and light-emittingdiodes (LED) along with CIGS TFPV. Also, there are concerns about thetoxicity of Cd throughout the lifecycle of the CdTe TFPV solar modules.Efforts to develop devices that leverage manufacturing and R&Dinfrastructure related to these TFPV technologies but using more widelyavailable and more environmentally friendly materials should beconsidered a top priority for research. The knowledge and infrastructuredeveloped around CdTe and CIGS TFPV technologies can be leveraged toallow faster adoption of new TFPV materials systems.

The development of TFPV devices exploiting Earth abundant materialsrepresents a daunting challenge in terms of thetime-to-commercialization. That same development also suggests anenticing opportunity for breakthrough discoveries. A quaternary systemsuch as CIGS requires management of multiple kinetic pathways,thermodynamic phase equilibrium considerations, defect chemistries, andinterfacial control. The vast phase-space to be managed includes processparameters, source material choices, compositions, and overallintegration schemes. The complexity of the intrinsically-doped,self-compensating, multinary, polycrystalline, queue-time-sensitive,thin-film absorber (CIGS), and its interfaces to up-, and down-streamprocessing, combined with the lack of knowledge on a device level toaddress efficiency losses effectively, makes it a highly empiricalmaterial system. The performance of any thin-film,(opto-)electronically-active device is extremely sensitive to itsinterfaces. Interface engineering for electronically-active devices ishighly empirical. Traditional R&D methods are ill-equipped to addresssuch complexity, and the traditionally slow pace of R&D could limit anynew material from reaching industrial relevance when having to competewith the incrementally improving performance of already established TFPVfabrication lines, and continuously decreasing panel prices for moretraditional cSi PV technologies.

Due to the complexity of the material, cell structure, and manufacturingprocess, both the fundamental scientific understanding and large scalemanufacturability are yet to be realized for TFPV devices. As thephotovoltaic industry pushes to achieve grid parity, much faster andbroader investigation is needed to explore the material, device, andprocess windows for higher efficiency and a lower cost of manufacturingprocess. Efficient methods for forming different types of TFPV devicesthat can be evaluated are necessary.

In light of the above, there is a need in the art for an economicalmethod of creating CIGS absorber layers having a graded bandgap. Agraded bandgap allows for higher efficiency CIGS solar cells.

SUMMARY OF THE DISCLOSURE

The following summary of the invention is included in order to provide abasic understanding of some aspects and features of the invention. Thissummary is not an extensive overview of the invention and as such it isnot intended to particularly identify key or critical elements of theinvention or to delineate the scope of the invention. Its sole purposeis to present some concepts of the invention in a simplified form as aprelude to the more detailed description that is presented below.

In some embodiments, methods are disclosed for fabricating highefficiency CIGS solar cells including the deposition of amulti-component metal precursor film on a substrate. The substrate isthen inserted into a system suitable for exposing the precursor to achalcogen to form a chalcogenide TFPV absorber. One or more Naprecursors are used to deposit a Na-containing layer on the precursorfilm in the system. This method eliminates the use of dedicatedequipment and processes for introducing Na to the TFPV absorber.

BRIEF DESCRIPTION OF THE DRAWINGS

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. The drawings are not to scale and the relative dimensionsof various elements in the drawings are depicted schematically and notnecessarily to scale.

The techniques of the present invention can readily be understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIG. 1 is a schematic diagram for implementing combinatorial processingand evaluation.

FIG. 2 is a schematic diagram for illustrating various process sequencesusing combinatorial processing and evaluation.

FIG. 3 illustrates a schematic diagram of a simple substrate TFPV stackaccording to an embodiment described herein.

FIG. 4 illustrates a schematic diagram of a simple superstrate TFPVstack according to an embodiment described herein.

FIG. 5 illustrates a schematic diagram of a simple superstrate TFPVstack according to an embodiment described herein.

FIG. 6 illustrates a flow chart according to some embodiments.

FIG. 7 illustrates a flow chart according to some embodiments.

FIG. 8 illustrates a diagram depicting the temperature, temperatureuniformity, gas flows, and chamber pressure during a selenizationprocess according to some embodiments.

FIG. 9 illustrates a diagram depicting the temperature, gas flows, andchamber pressure during a selenization process according to someembodiments.

FIG. 10 illustrates a flow chart according to some embodiments.

FIG. 11 illustrates a flow chart according to some embodiments.

FIG. 12 present SEM micrographs of films formed according to someembodiments.

FIG. 13 presents x-ray diffraction data of films formed according tosome embodiments.

FIG. 14 presents SIMS data of films formed according to someembodiments.

FIG. 15 presents carrier concentration versus NaF thickness data offilms formed according to some embodiments.

FIG. 16 presents device performance versus NaF thickness data of filmsformed according to some embodiments.

FIG. 17A presents device performance versus NaF thickness data of filmsformed according to some embodiments.

FIG. 17B presents device performance versus NaF thickness data of filmsformed according to some embodiments.

FIG. 17C presents device performance versus NaF thickness data of filmsformed according to some embodiments.

FIG. 18 presents device performance versus NaF thickness data of filmsformed according to some embodiments.

DETAILED DESCRIPTION

A detailed description of one or more embodiments is provided belowalong with accompanying figures. The detailed description is provided inconnection with such embodiments, but is not limited to any particularexample. The scope is limited only by the claims and numerousalternatives, modifications, and equivalents are encompassed. Numerousspecific details are set forth in the following description in order toprovide a thorough understanding. These details are provided for thepurpose of example and the described techniques may be practicedaccording to the claims without some or all of these specific details.For the purpose of clarity, technical material that is known in thetechnical fields related to the embodiments has not been described indetail to avoid unnecessarily obscuring the description.

As used herein, “CIGS” will be understood to represent the entire rangeof related alloys denoted byCu_(z)In_((1−x))Ga_(x)S_((2+w)(1−y))Se_((2+w)y), where 0.5≦z≦1.5, 0≦x≦1,0≦y≦1, −0.2≦w≦5. Similarly, as noted above, other materials (i.e. Ag,Au, Te, etc.) may be incorporated into potential absorber layers, (withe.g. Ag replacing part or all of the Cu, and Te replacing part or all ofthe Se and/or S). Also as mentioned previously, any of these materialsmay be further doped with a suitable dopant. As used herein, “CIGSSe”,“CIGSe”, and “CIGS” will be defined as equivalent and will be usedinterchangeably and will include all compositions includingCu—In—Ga—Se—S, Cu—In—Ga—Se, and Cu—In—Ga—S. Furthermore, “CIGS” alsoincludes other IB-IIIA-VIA alloys, like (Ag,Cu)(In,Ga)(Se), or(Cu)(In,Ga)(S,Se,Te), and the like.

As used herein, the notation “(IIIA)” will be understood to representthe sum of the concentrations of all Group-IIIA elements. This notationwill be used herein in calculations of the composition ratios of variouselements. This notation will be understood to extend to each of theother Groups of the periodic table respectively (e.g. “(IA)”, “(IIA)”,“(IVA)”, “(VIA)”, “(IB)”, “(IIB)”, etc.).

As used herein, the notation “Cu—In—Ga” and “Cu(In, Ga)” will beunderstood to include a material containing these elements in any ratio.The notation is extendable to other materials and other elementalcombinations.

As used herein, the notation “Cu_(x)In_(y)Ga_(z)” will be understood toinclude a material containing these elements in a specific ratio givenby x, y, and z (e.g. Cu_(m)Ga₂₅ contains 75 atomic % Cu and 25 atomic %Ga). The notation is extendable to other materials and other elementalcombinations.

As used herein, the notation “(Ag,Cu)_(x)(In,Ga)_(y)(Se,S,Te)_(z)” willbe understood to include a material containing a total amount ofGroup-IB elements (i.e. Ag plus Cu, etc.) in a ratio given by “x”, atotal amount of Group-IIIA elements (i.e. In plus Ga), etc. in a ratiogiven by “y”, and a total amount of Group-VIA elements (i.e. Se plus Splus Te, etc.) in a ratio given by “z”. The notation is extendable toother materials and other elemental combinations.

As used herein, “metal chalcogenide” or “chalcogenide” will beunderstood to represent the entire range of related compounds denoted by“MX” where M represents one or more metal elements and X represents oneor more of the chalcogen elements (e.g. O, S, Se, or Te).

As used herein, “chalcogenize” and “chalcogenization” will be understoodto represent the process by which one or more metals are converted tochalcogenide compounds by exposing the one or more metals to a chalcogen(e.g. O, S, Se, or Te) at elevated temperature (e.g. between 100C and700C). Specifically, “selenization” will be understood to represent theprocess by which one or more metals are converted to selenide compoundsby exposing the one or more metals to a Se source at elevatedtemperature (e.g. between 100C and 700C). Specifically, “sulfurization”will be understood to represent the process by which one or more metalsare converted to sulfide compounds by exposing the one or more metals toa S source at elevated temperature (e.g. between 100C and 700C). Inaddition, “chalcogenize” or “chalcogenization” will be understood torepresent the process by which a metal precursor is either partially orcompletely converted to the final multinary chalcogenide compound(s).Similarly, “chalcogenize” or “chalcogenization” will be understood torepresent the process by which a precursor containing one or morechalcogenide materials with/without one or more elemental or alloymetals is converted to one or more dense, polycrystalline, desiredmultinary chalcogenide compound(s). It should be understood that themajority of the final film contains the desired multinary chalcogenidecompound(s), yet a minority of the material might not be converted tothe desired multinary chalcogenide compound(s).

As used herein, the terms “film” and “layer” will be understood torepresent a portion of a stack. They will be understood to cover both asingle layer as well as a multilayered structure (i.e. a nanolaminate).As used herein, these terms will be used synonymously and will beconsidered equivalent.

As used herein, “single grading” and “single gradient” will beunderstood to describe cases wherein a parameter varies throughout thethickness of a film or layer and further exhibits a smooth, quasilinearvariation. Examples of suitable parameters used herein will include theatomic concentration of a specific elemental species (i.e. compositionvariation) throughout the thickness of a film or layer, and bandgapenergy variation throughout the thickness of a film or layer.

As used herein, “double grading” and “double gradient” will beunderstood to describe cases wherein a parameter varies throughout thethickness of a film or layer and further exhibits a variation whereinthe value of the parameter is smaller toward the middle of the film orlayer with respect to either end of the film or layer. It is not arequirement that the value of the parameter be equivalent at the twoends of the film or layer. Examples of suitable parameters used hereinwill include the atomic concentration of a specific elemental species(i.e. composition variation) throughout the thickness of a film orlayer, and bandgap energy variation throughout the thickness of a filmor layer.

As used herein, “substrate configuration” will be understood to describecases wherein the TFPV stack is built sequentially on top of a substrateand the light is assumed to be incident upon the top of the TFPV stack.As used herein, an “n-substrate” configuration will be used to denotethat the n-type layer (i.e. buffer layer) is closest to the incidentlight. The n-substrate configuration is the most common. As used herein,a “p-substrate” configuration will be used to denote that the p-typelayer (i.e. absorber layer) is closest to the incident light.

As used herein, “superstate configuration” will be understood todescribe cases wherein the substrate faces the incident sunlight. Theconvention will be used wherein light is assumed to be incident upon thesubstrate. As used herein, an “n-superstate” configuration will be usedto denote that the n-type layer (i.e. buffer layer) is closest to theincident light. As used herein, a “p-superstrate” configuration will beused to denote that the p-type layer (i.e. absorber layer) is closest tothe incident light.

As used herein, “substrate” will be understood to generally be one offloat glass, low-iron glass, borosilicate glass, flexible glass,specialty glass for high temperature processing, stainless steel, carbonsteel, aluminum, copper, titanium, molybdenum, polyimide, plastics,cladded metal foils, etc. Furthermore, the substrates may be processedin many configurations such as single substrate processing, multiplesubstrate batch processing, in-line continuous processing, roll-to-rollprocessing, etc. in all of the methods and examples described herein.

As used herein, “precursor layer”, “precursor material”, “metalprecursor layer”, “metal precursor material”, etc. will be understood tobe equivalent and be understood to refer to a metal, metal alloy, metalchalcogenide, etc. layer and/or material that is first deposited andwill ultimately become the absorber layer of the TFPV device after fullchalcogenization and/or further processing.

As used herein, “absorber layer”, “absorber material”, etc. will beunderstood to be equivalent and be understood to refer to a layer and/ormaterial that is responsible for the charge generation in the TFPVdevice after full chalcogenization and/or further processing.

As used herein, the notations “Al:ZnO” and “ZnO:Al” will be understoodto be equivalent and will describe a material wherein the base materialis the metal oxide and the element separated by the colon, “:”, isconsidered a dopant. In this example, Al is a dopant in a base materialof zinc oxide. The notation is extendable to other materials and otherelemental combinations.

As used herein, a “bandgap-increasing metal” will be understood to be ametal element that increases the bandgap when substituted for an elementfrom the same periodic table Group in the absorber material. Forexample, substituting Ag for a portion of the Cu in a CIGS material willincrease the bandgap. For example, increasing the relative amount of Gaversus indium in a CIGS material will increase the bandgap. For example,substituting Ag for a portion of the Cu in a CZTS material will increasethe bandgap. For example, substituting Ge for a portion of the Sn in aCZTS material will increase the bandgap.

In various FIGURES below, a TFPV material stack is illustrated using asimple planar structure. Those skilled in the art will appreciate thatthe description and teachings to follow can be readily applied to anysimple or complex TFPV solar cell structure, (e.g. a stack with(non-)conformal non-planar layers for optimized photon management). Thedrawings are for illustrative purposes only and do not limit theapplication of the present invention.

“Double grading” the bandgap of the CIGS absorber is a method known inthe art to increase the efficiency of CIGS solar cells. In a CIGSabsorber layer that has a double-graded bandgap profile, the bandgap ofthe CIGS layer increases toward the front surface and toward the backsurface of the CIGS layer, with a bandgap minimum located in a centerregion of the CIGS layer. Double grading helps in reducing unwantedcharge carrier recombination. The increasing bandgap profile at the backsurface of the CIGS layer, (i.e., the absorber surface that is remotefrom the incident light in the substrate configuration), creates a backsurface field, which reduces recombination at the back surface andenhances carrier collection. Generally, in the disclosure to follow, thedescription will apply to the “n-substrate” configuration for economy oflanguage. However, those skilled in the art will understand that thedisclosure is also equally applicable to either of the “p-substrate” or“n, p-superstrate” configurations discussed previously.

Co-evaporation is one technique known in the art for producing adouble-graded bandgap in a CIGS absorber layer. The co-evaporationprocess can produce a “gallium (Ga) rich region” (i.e. increased Garelative to the center region of the layer) at the front and/or backsurfaces of a CIGS absorber layer and a gallium-poor region in thecenter of the CIGS absorber layer. However, co-evaporation is arelatively complex process that is not as economical or as easilyimplemented as other deposition processes known in the art. In a 2-stepprocess, Cu—In—Ga metal precursors are deposited first, followed by asecond selenization process to form a CIGS absorber layer. The 2-stepprocess is generally more suited to large-scale low-cost manufacturingcompared to the co-evaporation process. However, because galliumselenizes slower than indium under otherwise identical conditions,gallium tends to accumulate towards the back surface of the CIGS layerduring the selenization process, thereby creating an uncontrolled singlegrading in the bandgap profile, i.e., the bandgap of the CIGS layerincreases from the front surface to the back surface. Double grading ofthe bandgap profile is then typically achieved by the incorporation ofsulfur (S) at the front surface of the CIGS layer for a 2-step processthereby creating CIGSSe. However, sulfur incorporation adds considerablecomplexity to the growth process and more easily produces a TFPVabsorber material (copper-indium-gallium-selenium-sulfur) of lowerquality compared to CIGSe without sulfur.

The efficiency of TFPV devices depends on many properties of theabsorber layer and the buffer layer such as crystallinity, grain size,composition uniformity, density, defect concentration, doping level,surface roughness, etc.

The manufacture of TFPV devices entails the integration and sequencingof many unit processing steps. As an example, TFPV manufacturingtypically includes a series of processing steps such as cleaning,surface preparation, deposition, patterning, etching, thermal annealing,and other related unit processing steps. The precise sequencing andintegration of the unit processing steps enables the formation offunctional devices meeting desired performance metrics such asefficiency, power production, and reliability.

As part of the discovery, optimization and qualification of each unitprocess, it is desirable to be able to i) test different materials, ii)test different processing conditions within each unit process module,iii) test different sequencing and integration of processing moduleswithin an integrated processing tool, iv) test different sequencing ofprocessing tools in executing different process sequence integrationflows, and combinations thereof in the manufacture of devices such asTFPV devices. In particular, there is a need to be able to test i) morethan one material, ii) more than one processing condition, iii) morethan one sequence of processing conditions, iv) more than one processsequence integration flow, and combinations thereof, collectively knownas “combinatorial process sequence integration”, on a single substratewithout the need of consuming the equivalent number of monolithicsubstrates per material(s), processing condition(s), sequence(s) ofprocessing conditions, sequence(s) of processes, and combinationsthereof. This can greatly improve both the speed and reduce the costsassociated with the discovery, implementation, optimization, andqualification of material(s), process(es), and process integrationsequence(s) required for manufacturing.

Systems and methods for High Productivity Combinatorial (HPC) processingare described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S.Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filedon May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S.Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all hereinincorporated by reference. Systems and methods for HPC processing arefurther described in U.S. patent application Ser. No. 11/352,077 filedon Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patentapplication Ser. No. 11/419,174 filed on May 18, 2006, claiming priorityfrom Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed onFeb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patentapplication Ser. No. 11/674,137 filed on Feb. 12, 2007, claimingpriority from Oct. 15, 2005 which are all herein incorporated byreference.

HPC processing techniques have been successfully adapted to wet chemicalprocessing such as etching, texturing, polishing, cleaning, etc. HPCprocessing techniques have also been successfully adapted to depositionprocesses such as sputtering, atomic layer deposition (ALD), andchemical vapor deposition (CVD).

HPC processing techniques have been adapted to the development andinvestigation of absorber layers and buffer layers for TFPV solar cellsas described in U.S. application Ser. No. 13/236,430 filed on Sep. 19,2011, entitled “COMBINATORIAL METHODS FOR DEVELOPING SUPERSTRATE THINFILM SOLAR CELLS” and is incorporated herein by reference. However, HPCprocessing techniques have not been successfully adapted to thedevelopment of contact structures for TFPV devices. Generally, there aretwo basic configurations for TFPV devices. The first configuration isknown as a “substrate” configuration. In this configuration, the contactthat is formed on or near the substrate is called the back contact. Inthis configuration, the light is incident on the TFPV device from thetop of the material stack (i.e. the side opposite the substrate). CIGSTFPV devices are most commonly manufactured in this configuration. Thesecond configuration is known as a “superstrate” configuration. In thisconfiguration, the contact that is formed on or near the substrate iscalled the front contact. In this configuration, the light is incidenton the TFPV device through the substrate. CdTe, and a-Si, TFPV devicesare most commonly manufactured in this configuration. In bothconfigurations, light trapping schemes may be implemented in the contactlayer that is formed on or near the substrate. Additionally, otherefficiency or durability improvements can be implemented in the contactlayer that is formed farthest away from the substrate.

FIG. 1 illustrates a schematic diagram, 100, for implementingcombinatorial processing and evaluation using primary, secondary, andtertiary screening. The schematic diagram, 100, illustrates that therelative number of combinatorial processes run with a group ofsubstrates decreases as certain materials and/or processes are selected.Generally, combinatorial processing includes performing a large numberof processes during a primary screen, selecting promising candidatesfrom those processes, performing the selected processing during asecondary screen, selecting promising candidates from the secondaryscreen for a tertiary screen, and so on. In addition, feedback fromlater stages to earlier stages can be used to refine the successcriteria and provide better screening results.

For example, thousands of materials are evaluated during a materialsdiscovery stage, 102. Materials discovery stage, 102, is also known as aprimary screening stage performed using primary screening techniques.Primary screening techniques may include dividing substrates intocoupons and depositing materials using varied processes. The materialsare then evaluated, and promising candidates are advanced to thesecondary screen, or materials and process development stage, 104.Evaluation of the materials is performed using metrology tools such aselectronic testers and imaging tools (i.e., microscopes).

The materials and process development stage, 104, may evaluate hundredsof materials (i.e., a magnitude smaller than the primary stage) and mayfocus on the processes used to deposit or develop those materials.Promising materials and processes are again selected, and advanced tothe tertiary screen or process integration stage, 106, where tens ofmaterials and/or processes and combinations are evaluated. The tertiaryscreen or process integration stage, 106, may focus on integrating theselected processes and materials with other processes and materials.

The most promising materials and processes from the tertiary screen areadvanced to device qualification, 108. In device qualification, thematerials and processes selected are evaluated for high volumemanufacturing, which normally is conducted on full substrates withinproduction tools, but need not be conducted in such a manner. Theresults are evaluated to determine the efficacy of the selectedmaterials and processes. If successful, the use of the screenedmaterials and processes can proceed to pilot manufacturing, 110.

The schematic diagram, 100, is an example of various techniques that maybe used to evaluate and select materials and processes for thedevelopment of new materials and processes. The descriptions of primary,secondary, etc. screening and the various stages, 102-110, are arbitraryand the stages may overlap, occur out of sequence, be described and beperformed in many other ways.

This application benefits from High Productivity Combinatorial (HPC)techniques described in U.S. patent application Ser. No. 11/674,137filed on Feb. 12, 2007 which is hereby incorporated for reference in itsentirety. Portions of the '137 application have been reproduced below toenhance the understanding of the present invention. The embodimentsdescribed herein enable the application of combinatorial techniques toprocess sequence integration in order to arrive at a globally optimalsequence of TFPV manufacturing operations by considering interactioneffects between the unit manufacturing operations, the processconditions used to effect such unit manufacturing operations, hardwaredetails used during the processing, as well as materials characteristicsof components utilized within the unit manufacturing operations. Ratherthan only considering a series of local optimums, i.e., where the bestconditions and materials for each manufacturing unit operation isconsidered in isolation, the embodiments described below considerinteractions effects introduced due to the multitude of processingoperations that are performed and the order in which such multitude ofprocessing operations are performed when fabricating a TFPV device. Aglobal optimum sequence order is therefore derived and as part of thisderivation, the unit processes, unit process parameters and materialsused in the unit process operations of the optimum sequence order arealso considered.

The embodiments described further analyze a portion or sub-set of theoverall process sequence used to manufacture a TFPV device. Once thesubset of the process sequence is identified for analysis, combinatorialprocess sequence integration testing is performed to optimize thematerials, unit processes, hardware details, and process sequence usedto build that portion of the device or structure. During the processingof some embodiments described herein, structures are formed on theprocessed substrate that are equivalent to the structures formed duringactual production of the TFPV device. For example, such structures mayinclude, but would not be limited to, contact layers, buffer layers,absorber layers, or any other series of layers or unit processes thatcreate an intermediate structure found on TFPV devices. While thecombinatorial processing varies certain materials, unit processes,hardware details, or process sequences, the composition or thickness ofthe layers or structures or the action of the unit process, such ascleaning, surface preparation, deposition, surface treatment, etc. issubstantially uniform through each discrete region. Furthermore, whiledifferent materials or unit processes may be used for correspondinglayers or steps in the formation of a structure in different regions ofthe substrate during the combinatorial processing, the application ofeach layer or use of a given unit process is substantially consistent oruniform throughout the different regions in which it is intentionallyapplied. Thus, the processing is uniform within a region (inter-regionuniformity) and between regions (intra-region uniformity), as desired.It should be noted that the process can be varied between regions, forexample, where a thickness of a layer is varied or a material may bevaried between the regions, etc., as desired by the design of theexperiment.

The result is a series of regions on the substrate that containstructures or unit process sequences that have been uniformly appliedwithin that region and, as applicable, across different regions. Thisprocess uniformity allows comparison of the properties within and acrossthe different regions such that the variations in test results are dueto the varied parameter (e.g., materials, unit processes, unit processparameters, hardware details, or process sequences) and not the lack ofprocess uniformity. In the embodiments described herein, the positionsof the discrete regions on the substrate can be defined as needed, butare preferably systematized for ease of tooling and design ofexperimentation. In addition, the number, variants and location ofstructures within each region are designed to enable valid statisticalanalysis of the test results within each region and across regions to beperformed.

FIG. 2 is a simplified schematic diagram illustrating a generalmethodology for combinatorial process sequence integration that includessite isolated processing and/or conventional processing in accordancewith one embodiment of the invention. In one embodiment, the substrateis initially processed using conventional process N. In one exemplaryembodiment, the substrate is then processed using site isolated processN+1. During site isolated processing, an HPC module may be used, such asthe HPC module described in U.S. patent application Ser. No. 11/352,077filed on Feb. 10, 2006. The substrate can then be processed using siteisolated process N+2, and thereafter processed using conventionalprocess N+3. Testing is performed and the results are evaluated. Thetesting can include physical, chemical, acoustic, magnetic, electrical,optical, etc. tests. From this evaluation, a particular process from thevarious site isolated processes (e.g. from steps N+1 and N+2) may beselected and fixed so that additional combinatorial process sequenceintegration may be performed using site isolated processing for eitherprocess N or N+3. For example, a next process sequence can includeprocessing the substrate using site isolated process N, conventionalprocessing for processes N+1, N+2, and N+3, with testing performedthereafter.

It should be appreciated that various other combinations of conventionaland combinatorial processes can be included in the processing sequencewith regard to FIG. 2. That is, the combinatorial process sequenceintegration can be applied to any desired segments and/or portions of anoverall process flow. The combinatorial processing may employ uniformprocessing of site isolated regions or may employ gradient techniques.Characterization, including physical, chemical, acoustic, magnetic,electrical, optical, etc. testing, can be performed after each processoperation, and/or series of process operations within the process flowas desired. The feedback provided by the testing is used to selectcertain materials, processes, process conditions, and process sequencesand eliminate others. Furthermore, the above flows can be applied toentire monolithic substrates, or portions of monolithic substrates suchas coupons.

Under combinatorial processing operations the processing conditions atdifferent regions can be controlled independently. Consequently, processmaterial amounts, reactant species, processing temperatures, processingtimes, processing pressures, processing flow rates, processing powers,processing reagent compositions, the rates at which the reactions arequenched, deposition order of process materials, process sequence steps,hardware details, etc., can be varied from region to region on thesubstrate. Thus, for example, when exploring materials, a processingmaterial delivered to a first and second region can be the same ordifferent. If the processing material delivered to the first region isthe same as the processing material delivered to the second region, thisprocessing material can be offered to the first and second regions onthe substrate at different concentrations. In addition, the material canbe deposited under different processing parameters. Parameters which canbe varied include, but are not limited to, process material amounts,reactant species, processing temperatures, processing times, processingpressures, processing flow rates, processing powers, processing reagentcompositions, the rates at which the reactions are quenched, atmospheresin which the processes are conducted, an order in which materials aredeposited, hardware details of the gas distribution assembly, etc. Itshould be appreciated that these process parameters are exemplary andnot meant to be an exhaustive list as other process parameters commonlyused in TFPV manufacturing may be varied.

As mentioned above, within a region, the process conditions aresubstantially uniform. That is, the embodiments, described hereinlocally perform the processing in a conventional manner, e.g.,substantially consistent and substantially uniform, while globally overthe substrate, the materials, processes, and process sequences may vary.Thus, the testing will find optimums without interference from processvariation differences between processes that are meant to be the same.However, in some embodiments, the processing may result in a gradientwithin the regions. It should be appreciated that a region may beadjacent to another region in one embodiment or the regions may beisolated and, therefore, non-overlapping. When the regions are adjacent,there may be a slight overlap wherein the materials or precise processinteractions are not known, however, a portion of the regions, normallyat least 50% or more of the area, is uniform and all testing occurswithin that region. Further, the potential overlap is only allowed withmaterial of processes that will not adversely affect the result of thetests. Both types of regions are referred to herein as regions ordiscrete regions.

FIG. 3 illustrates a schematic diagram of a simple TFPV device stack inthe substrate configuration consistent with some embodiments of thepresent invention. The convention will be used wherein light is assumedto be incident upon the top of the material stack in the substrateconfiguration as illustrated. This generic diagram would be typical of aCIGS TFPV device. A back contact layer, 304, is formed on a substrate,302. Examples of suitable substrates comprise float glass, low-ironglass, borosilicate glass, flexible glass, specialty glass for hightemperature processing, stainless steel, carbon steel, aluminum, copper,titanium, molybdenum, polyimide, plastics, cladded metal foils, etc.Furthermore, the substrates may be processed in many configurations suchas single substrate processing, multiple substrate batch processing,in-line continuous processing, roll-to-roll processing, etc. As usedherein, the phrase “back contact” will be understood to be the primarycurrent conductor layer situated between the substrate and the absorberlayer in a substrate configuration TFPV device. An example of a commonback contact layer material is Mo for CIGS TFPV devices. Other types ofTFPV devices use different materials for the back contact. As anexample, Cu alloys such as Cu/Au, Cu/graphite, Cu/Mo, Cu:ZnTe, etc. aretypically used for CdTe TFPV devices and transparent conductive oxide(TCO) materials such as ZnO, ITO, SnO₂:F, etc. are typically used fora-Si TFPV devices. The back contact layer may be formed by any number ofdeposition technologies. Examples of suitable deposition technologiescomprise physical vapor deposition (PVD) (e.g. sputtering), evaporation,chemical vapor deposition (CVD), atomic layer deposition (ALD), plating,printing, wet coating, etc. The thickness of the back contact layer istypically between about 0.3 um and about 1.0 um. The back contact layerhas a number of requirements such as high conductivity, good ohmiccontact to the absorber layer, ease of bonding to tabs for externalconnectivity, ease of scribing or other removal, good thermo-mechanicalstability, and chemical resistance during subsequent processing, amongothers.

Optionally, a diffusion barrier and/or adhesion-promotion layer (notshown) may be formed between the substrate and the back contact layer.When implemented, the diffusion barrier layer stops the diffusion ofimpurities from the substrate into the back contact layer, oralternatively, stops the diffusion and reaction of the back contactmaterial with the substrate. Examples of common diffusion barrier and/oradhesion-promotion layers comprise chromium, vanadium, tungsten,nitrides such as tantalum nitride, tungsten nitride, titanium nitride,silicon nitride, zirconium nitride, hafnium nitride, oxy-nitrides suchas tantalum oxy-nitride, tungsten oxy-nitride, titanium oxy-nitride,silicon oxy-nitride, zirconium oxy-nitride, hafnium oxy-nitride, oxidessuch as aluminum oxide, silicon oxide, carbides such as silicon carbide,binary and/or multinary compounds of tungsten, titanium, molybdenum,chromium, vanadium, tantalum, hafnium, zirconium, and/or niobiumwith/without the inclusion of nitrogen and/or oxygen. The diffusionbarrier layer may be formed, partially or completely, from any wellknown technique such as sputtering, ALD, CVD, evaporation, wet methodssuch as printing or spraying of inks, screen printing, inkjet printing,slot die coating, gravure printing, wet chemical depositions, or fromsol-gel methods, such as the coating, drying, and firing ofpolysilazanes.

A p-type absorber layer, 306, of CIGS is then deposited on top of theback contact layer. The absorber layer may be formed, partially orcompletely, using a variety of techniques such as PVD (sputtering),co-evaporation, in-line evaporation, plating, printing or spraying ofinks, screen printing, inkjet printing, slot die coating, gravureprinting, wet chemical depositions, CVD, etc. Advantageously, theabsorber layer is deficient in Cu. The Cu deficiency may be controlledby managing the deposition conditions. Advantageously, a small amount ofNa is present during the absorber growth. The Na may be added byout-diffusion from the SLG substrate or may be purposely added in theform of Na₂Se, NaF, sodium alloys of In and/or Ga, or another Na source,prior, during, or after the deposition and/or growth of the absorberlayer. Optionally, the precursor and/or absorber layer undergoes aselenization process after formation to convert the precursor to CIGSinto a high-quality CIGS semiconductor film. The selenization processinvolves the exposure of the precursor and/or absorber layer to H₂Se,H₂S, Se vapor, S vapor, or diethylselenide (DESe) at temperatures mosttypically between about 300C and 700C. It should be noted that theprecursor to CIGS might already contain a chalcogen source (e.g. Se),either as a separate layer, or incorporated into the bulk of theprecursor layer. The precursor film can be a stack of layers, or onelayer. The precursor layer can be dense, or porous. The precursor filmtypically contains Cu, In, and Ga. The precursor layer is most commonlydeposited by sputtering from e.g. binary copper-gallium and Indiumsputter targets. Nevertheless, plating and printing to deposit the metalprecursor film containing Cu, In, and/or Ga are used as well. During theselenization process, a layer of Mo(S,Se)₂ (not shown) forms at the backcontact/absorber layer interface and forms a fairly good ohmic contactbetween the two layers. Alternatively, a layer of Mo(S,Se)₂ (not shown)can be deposited at the back contact/absorber layer interface using avariety of well known techniques such as PVD (sputtering), CBD, ALD,plating, etc. The thickness of the absorber layer is typically betweenabout 1.0 um and about 3.0 um. The performance of the absorber layer issensitive to materials properties such as crystallinity, grain size,surface roughness, composition, defect concentration, etc. as well asprocessing parameters such as temperature, deposition rate, thermaltreatments, etc.

An n-type buffer layer, 308, is then deposited on top of the absorberlayer. Examples of suitable n-type buffer layers comprise CdS, ZnS,In₂S₃, In₂(S,Se)₃, CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is thematerial most often used as the n-type buffer layer in CIGS TFPVdevices. The buffer layer may be deposited using chemical bathdeposition (CBD), chemical surface deposition (CSD), PVD (sputtering),printing, plating, ALD, Ion-Layer-Gas-Reaction (ILGAR), ultrasonicspraying, or evaporation. The thickness of the buffer layer is typicallybetween about 30 nm and about 100 nm. The performance of the bufferlayer is sensitive to materials properties such as crystallinity, grainsize, surface roughness, composition, defect concentration, etc. as wellas processing parameters such as temperature, deposition rate, thermaltreatments, etc.

Optionally, an intrinsic ZnO (iZnO) layer, 310, is then formed on top ofthe buffer layer. The iZnO layer is a high resistivity material andforms part of the transparent conductive oxide (TCO) stack that servesas part of the front contact structure. The TCO stack is formed fromtransparent conductive metal oxide materials and collects charge acrossthe face of the TFPV solar cell and conducts the charge to tabs used toconnect the solar cell to external loads. The iZnO layer makes the TFPVsolar cell less sensitive to lateral non-uniformities caused bydifferences in composition or defect concentration in the absorberand/or buffer layers. The iZnO layer is typically between about 0 nm and150 nm in thickness. The iZnO layer is typically formed using a(reactive) PVD (sputtering) technique or CVD technique, but can bedeposited by plating or printing as well. A low resistivity top TCOlayer, 312, (examples include Al:ZnO (AZO), InSnO (ITO), InZnO, B:ZnO,Ga:ZnO, F:ZnO, F:SnO₂, etc.) is formed on top of the iZnO layer. The topTCO layer is typically between about 0.25 um and 1.0 um in thickness.The top TCO layer is typically formed using a (reactive) PVD(sputtering) technique or CVD technique. Optionally, the transparent topelectrode can be printed or wet-coated from (silver) nano-wires, carbonnanotubes, and the like.

FIG. 4 illustrates a simple CIGS TFPV device material stack, 400,consistent with some embodiments of the present invention. The CIGS TFPVdevice illustrated in FIG. 4 is shown in a superstrate configurationwherein the glass substrate faces the incident sunlight. The conventionwill be used wherein light is assumed to be incident upon the substrateand material stack as illustrated. As used herein, this configurationwill be labeled an “n-superstrate” configuration to denote that then-type layer (i.e. buffer layer) is closest to the incident light. Thislabel is to distinguish the configuration from an alternateconfiguration described with respect to FIG. 5 below. The formation ofthe CIGS TFPV device will be described starting with the substrate.Examples of suitable substrates comprise float glass, low-iron glass,borosilicate glass, flexible glass, specialty glass for high temperatureprocessing, polyimide, plastics, etc. Furthermore, the substrates may beprocessed in many configurations such as single substrate processing,multiple substrate batch processing, in-line continuous processing,roll-to-roll processing, etc.

A low resistivity bottom TCO front contact layer, 404, (examples includeAl:ZnO (AZO), InSnO (ITO), InZnO, B:ZnO, Ga:ZnO, F:ZnO, F:SnO₂, etc.) isformed on top of the substrate, 402. As used herein, the phrase “frontcontact” will be understood to be the primary current conductor layersituated between the substrate and the buffer layer in a superstrateconfiguration TFPV device. The bottom TCO layer is typically betweenabout 0.3 um and 2.0 um in thickness. The bottom TCO layer is typicallyformed using a reactive PVD (sputtering) technique or CVD technique.

Optionally, a diffusion barrier and/or adhesion-promotion layer (notshown) may be formed between the substrate, 402, and the front contactlayer, 404. When implemented, the diffusion barrier layer stops thediffusion of impurities from the substrate into the TCO, oralternatively, stops the diffusion and reaction of the TCO material andabove layers with the substrate. Examples of common diffusion barrierand/or adhesion-promotion layers comprise chromium, vanadium, tungsten,nitrides such as tantalum nitride, tungsten nitride, titanium nitride,silicon nitride, zirconium nitride, hafnium nitride, oxy-nitrides suchas tantalum oxy-nitride, tungsten oxy-nitride, titanium oxy-nitride,silicon oxy-nitride, zirconium oxy-nitride, hafnium oxy-nitride, oxidessuch as aluminum oxide, silicon oxide, carbides such as silicon carbide,binary and/or multinary compounds of tungsten, titanium, molybdenum,chromium, vanadium, tantalum, hafnium, zirconium, and/or niobiumwith/without the inclusion of nitrogen and/or oxygen. It should beunderstood that the diffusion barrier layer composition and thicknessare optimized for optical transparency as necessary for the superstrateconfiguration. The diffusion barrier layer may be formed from any wellknown technique such as sputtering, ALD, CVD, evaporation, wet methodssuch as printing or spraying of inks, screen printing, inkjet printing,slot die coating, gravure printing, wet chemical depositions, or fromsol-gel methods, such as the coating, drying, and firing ofpolysilazanes.

An intrinsic iZnO layer, 406, is then formed on top of the TCO layer.The iZnO layer is a high resistivity material and forms part of thetransparent conductive oxide (TCO) stack that serves as part of thefront contact structure. The iZnO layer makes the TFPV device lesssensitive to lateral non-uniformities caused by differences incomposition or defect concentration in the absorber and/or bufferlayers. The iZnO layer is typically between about 0 nm and 150 nm inthickness. The iZnO layer is typically formed using a reactive PVD(sputtering) technique or CVD technique.

An n-type buffer layer, 408, is then deposited on top of the iZnO layer,406. Examples of suitable n-type buffer layers comprise CdS, ZnS, In₂S₃,In₂(S,Se)₃, CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is the material mostoften used as the n-type buffer layer in CIGS TFPV devices. The bufferlayer may be deposited using chemical bath deposition (CBD), chemicalsurface deposition (CSD), PVD (sputtering), printing, plating, ALD,Ion-Layer-Gas-Reaction (ILGAR), ultrasonic spraying, or evaporation. Thethickness of the buffer layer is typically between about 30 nm and about100 nm. The performance of the buffer layer is sensitive to materialsproperties such as crystallinity, grain size, surface roughness,composition, defect concentration, etc. as well as processing parameterssuch as temperature, deposition rate, thermal treatments, etc.

A p-type absorber layer, 410, of CIGS is then deposited on top of thebuffer layer. The absorber layer may be formed, partially or completely,using a variety of techniques such as PVD (sputtering), co-evaporation,in-line evaporation, plating, printing or spraying of inks, screenprinting, inkjet printing, slot die coating, gravure printing, wetchemical depositions, CVD, etc. Advantageously, the absorber layer isdeficient in Cu. The Cu deficiency may be controlled by managing thedeposition conditions. Advantageously, a small amount of Na is presentduring the growth of the absorber. The Na may be purposely added in theform of Na₂Se or another Na source, prior, during, or after thedeposition and/or growth of the absorber layer. Optionally, theprecursor and/or absorber layer undergoes a selenization process afterformation to convert the precursor to CIGS into a high-quality CIGSsemiconductor film. The selenization process involves the exposure ofthe precursor and/or absorber layer to H₂Se, H₂S, Se vapor, S vapor, ordiethylselenide (DESe) at temperatures most typically between about 300Cand 700C. It should be noted that the precursor to CIGS might alreadycontain a chalcogen source (e.g. Se), either as a separate layer, orincorporated into the bulk of the precursor layer. The precursor filmcan be a stack of layers, or one layer. The precursor layer can bedense, or porous. The precursor film typically contains Cu, In, and Ga.The precursor layer is most commonly deposited by sputtering from e.g.binary Cu—Ga and In sputter targets. Nevertheless, plating and printingto deposit the metal precursor film containing Cu, In, and/or Ga areused as well. During subsequent processing, a layer of Mo(S,Se)₂ (notshown) is formed at the back contact/absorber layer interface and formsa fairly good ohmic contact between the two layers. The thickness of theabsorber layer is typically between about 1.0 um and about 3.0 um. Theperformance of the absorber layer is sensitive to materials propertiessuch as crystallinity, grain size, surface roughness, composition,defect concentration, etc. as well as processing parameters such astemperature, deposition rate, thermal treatments, etc.

A back contact layer, 412, is formed on absorber layer, 410. An exampleof a common back contact layer material is Mo for CIGS TFPV devices. Theback contact layer may be formed by any number of depositiontechnologies. Examples of suitable deposition technologies comprise PVD(sputtering), evaporation, chemical vapor deposition (CVD), atomic layerdeposition (ALD), plating, etc. The thickness of the back contact layeris typically between about 0.3 um and about 1.0 um. The back contactlayer has a number of requirements such as high conductivity, good ohmiccontact to the absorber layer, ease of bonding to tabs for externalconnectivity, ease of scribing or other removal, good thermo-mechanicalstability, and chemical resistance during subsequent processing, amongothers. Other types of TFPV devices use different materials for the backcontact. As an example, Cu alloys such as Cu/Au, Cu/graphite, Cu/Mo,Cu:ZnTe, etc. are typically used for CdTe TFPV devices and TCO materialssuch as ZnO, ITO, SnO₂:F, etc. are typically used for a-Si TFPV devices.

FIG. 5 illustrates a simple CIGS TFPV device material stack, 500,consistent with some embodiments of the present invention. The CIGS TFPVdevice illustrated in FIG. 5 is shown in a superstrate configurationwherein the glass substrate faces the incident sunlight. The conventionwill be used wherein light is assumed to be incident upon the substrateand material stack as illustrated. As used herein, this configurationwill be labeled a “p-superstrate” configuration to denote that thep-type layer (i.e. absorber layer) is closest to the incident light.This label is to distinguish the configuration from the alternateconfiguration described with respect to FIG. 4 previously. The formationof the CIGS TFPV device will be described starting with the substrate.Examples of suitable substrates comprise float glass, low-iron glass,borosilicate glass, flexible glass, specialty glass for high temperatureprocessing, polyimide, plastics, etc. Furthermore, the substrates may beprocessed in many configurations such as single substrate processing,multiple substrate batch processing, in-line continuous processing,roll-to-roll processing, etc.

A low resistivity bottom TCO front contact layer (examples includeAl:ZnO (AZO), InSnO (ITO), InZnO, B:ZnO, Ga:ZnO, F:ZnO, F:SnO₂, etc.),504, is formed on top of the substrate, 502. As used herein, the phrase“front contact” will be understood to be the primary current conductorlayer situated between the substrate and the absorber layer in asuperstrate configuration TFPV device. The bottom TCO layer is typicallybetween about 0.3 um and 2.0 um in thickness. The bottom TCO layer istypically formed using a reactive PVD (sputtering) technique or CVDtechnique. The TCO can be a p-type TCO, (e.g. ternary-based oxide in thefamily of Co₃O₄-based spinels, like Co₂ZnO₄ and Co₂NiO₄). Nevertheless,it should be understood that an n-type TCO with an additional layer(e.g. a heavily-doped p-type semiconductor layer, or MoSe₂) between theTCO and the absorber can be used as well. Furthermore, the TCO might bea bi- or multi-layer of an n-type TCO in contact with the substrate,followed by an ultrathin metal layer, (e.g. like Ag), followed by a thinp-type TCO in contact with the absorber layer, with/without anadditional MoSe₂ layer between the p-type TCO and the absorber layer.

Optionally, a diffusion barrier and/or adhesion-promotion layer (notshown) may be formed between the substrate, 502, and the front contactlayer. 504. When implemented, the diffusion barrier and/oradhesion-promotion layer stops the diffusion of impurities from thesubstrate into the TCO, or alternatively, stops the diffusion andreaction of the TCO material and above layers with the substrate.Examples of common diffusion barrier and/or adhesion-promotion layerscomprise chromium, vanadium, tungsten, nitrides such as tantalumnitride, tungsten nitride, titanium nitride, silicon nitride, zirconiumnitride, hafnium nitride, oxy-nitrides such as tantalum oxy-nitride,tungsten oxy-nitride, titanium oxy-nitride, silicon oxy-nitride,zirconium oxy-nitride, hafnium oxy-nitride, oxides such as aluminumoxide, silicon oxide, carbides such as silicon carbide, binary and/ormultinary compounds of tungsten, titanium, molybdenum, chromium,vanadium, tantalum, hafnium, zirconium, and/or niobium with/without theinclusion of nitrogen and/or oxygen. It should be understood that thediffusion barrier and/or adhesion-promotion layer composition andthickness are optimized for optical transparency as necessary for thesuperstrate configuration. The diffusion barrier and/oradhesion-promotion layer may be formed from any well known techniquesuch as sputtering, ALD, CVD, evaporation, wet methods such as printingor spraying of inks, screen printing, inkjet printing, slot die coating,gravure printing, wet chemical depositions, or from sol-gel methods suchas the coating, drying, and firing of polysilazanes.

A p-type absorber layer, 506, of CIGS is then deposited on top of thefront contact layer. The absorber layer may be formed, partially, orcompletely, using a variety of techniques such as PVD (sputtering),co-evaporation, in-line evaporation, plating, printing or spraying ofinks, screen printing, inkjet printing, slot die coating, gravureprinting, wet chemical depositions, CVD, etc. Advantageously, theabsorber layer is deficient in Cu. The Cu deficiency may be controlledby managing the deposition conditions. Advantageously, a small amount ofNa is present during the growth of the absorber. The Na may be purposelyadded in the form of Na₂Se or another Na source, prior, during, or afterthe deposition of the precursor and/or absorber layer. Typically, theprecursor and/or absorber layer undergoes a chalcogenization (e.g.selenization) process after formation to convert the precursor to CIGSinto a high-quality CIGS semiconductor film. The chalcogenizationprocess involves the exposure of the precursor and/or absorber layer toH₂Se, H₂S, Se vapor, S vapor, or diethylselenide (DESe) at temperaturesmost typically between about 300C and 700C. It should be noted that theprecursor to CIGS might already contain a chalcogen source (e.g. Se),either as a separate layer, or incorporated into the bulk of theprecursor layer. The precursor film can be a stack of layers, or onelayer. The precursor layer can be dense, or porous. The precursor filmtypically contains Cu, In, and Ga. The precursor layer is most commonlydeposited by sputtering from e.g. binary copper-gallium and Indiumsputter targets. Nevertheless, plating and printing to deposit the metalprecursor film containing Cu, In, and/or Ga are used as well. Thethickness of the absorber layer is typically between about 1.0 um andabout 3.0 um. The performance of the absorber layer is sensitive tomaterials properties such as crystallinity, grain size, surfaceroughness, composition, defect concentration, etc. as well as processingparameters such as temperature, deposition rate, thermal treatments,etc.

An n-type buffer layer, 508, is then deposited on top of the absorberlayer. Examples of suitable n-type buffer layers comprise CdS, ZnS,In₂S₃, In₂(S,Se)₃, CdZnS, ZnO, Zn(O,S), (Zn,Mg)O, etc. CdS is thematerial most often used as the n-type buffer layer in CIGS TFPVdevices. The buffer layer may be deposited using chemical bathdeposition (CBD), chemical surface deposition (CSD), PVD (sputtering),printing, plating, ALD, Ion-Layer-Gas-Reaction (ILGAR), ultrasonicspraying, or evaporation. The thickness of the buffer layer is typicallybetween about 30 nm and about 100 nm. The performance of the bufferlayer is sensitive to materials properties such as crystallinity, grainsize, surface roughness, composition, defect concentration, etc. as wellas processing parameters such as temperature, deposition rate, thermaltreatments, etc.

An intrinsic iZnO layer, 510, is then formed on top of the buffer layer.The iZnO layer is a high resistivity material and forms part of the backcontact structure. The iZnO layer makes the TFPV device less sensitiveto lateral non-uniformities caused by differences in composition ordefect concentration in the absorber and/or buffer layers. The iZnOlayer is typically between about 0 nm and 150 nm in thickness. The iZnOlayer is typically formed using a reactive PVD (sputtering) technique orCVD technique.

A back contact layer, 512, is formed on intrinsic iZnO layer, 510. Anexample of a suitable back contact layer material is a thin n-type TCOfollowed by Ni and/or Al. The back contact layer may be formed by anynumber of deposition technologies. Examples of suitable depositiontechnologies comprise PVD (sputtering), evaporation, chemical vapordeposition (CVD), atomic layer deposition (ALD), plating, etc. Thethickness of the back contact layer is typically between about 0.3 umand about 1.0 um. The back contact layer has a number of requirementssuch as high conductivity, good ohmic contact to the absorber layer,ease of bonding to tabs for external connectivity, ease of scribing orother removal, good thermo-mechanical stability, and chemical resistanceduring subsequent processing, among others. Other types of TFPV devicesuse different materials for the back contact. As an example, Cu alloyssuch as Cu/Au, Cu/graphite, Cu/Mo, Cu:ZnTe, etc. are typically used forCdTe TFPV devices and TCO materials such as ZnO, ITO, SnO₂:F, etc. aretypically used for a-Si TFPV devices.

The film stack described above is just one example of a film stack thatcan be used for TFPV devices. As an example, another substrate filmstack (i.e. similar configuration as FIG. 3) might be:substrate/AZO/Mo/CIGS/CdS/iZnO/AZO. As an example, another p-superstratefilm stack (i.e. similar configuration as FIG. 5) might be:substrate/barrier/ZnO:Al/Mo/CIGS/CdS/iZnO/ZnO:Al/Al. The detailed filmstack configuration is not meant to be limiting, but simply serves as anexample of the implementation of embodiments of the present invention.

The formation of the absorber layer is typically a multi-step process.One way of grading CIGS materials is by a 2-step approach as illustratedin FIG. 6. In step 602, “metal precursor” films are deposited. ForCIGS-like absorbers, the metal precursor films comprise Group IB andGroup-IIIA metals. In the case of CIGS absorbers, the metal precursorfilms comprise Cu, In, and Ga, with/without a Na source. This metal filmneeds to be converted to one or more chalcogenide compound(s) to formthe absorber layer. The metal precursor film is converted to one or morechalcogenide compound(s) by heating the film in the presence of a sourceof one or more Group-VIA elements as indicated in step 606. Optionally,the chalcogenide film can be annealed as indicated in step 608. ForCIGS-type absorbers, a variation of the 2-step process comprisesdepositing a second thin Group-IIIA-containing film or Group-IIIAchalcogenide material (e.g. Ga—Se, or Al—Se) on top of the metalprecursor film as illustrated in step 604. The Group-IIIA metal is boundin the chalcogenide, its diffusion (e.g. Ga, or Al) toward the back ofthe absorber layer is retarded, yielding a higher concentration of theGroup-IIIA metal at the front of the absorber layer. This results in adouble-graded composition of the Group-IIIA metal and a double-gradedbandgap.

Generally, the 2-step method may comprise more than two steps whenvarious wet chemical and/or conversion methods (e.g. for densificationor contaminant removal) and/or deposition steps (e.g. for a separatechalcogen layer as discussed previously) are used to form the metalprecursor film. As discussed above, the metal precursor film may be asingle layer or may be formed from multiple layers, it may be dense orporous.

The highest efficiencies for 2-step CIG(S)Se have been achieved byconverting PVD (sputtered) Cu(In,Ga) into CIG(S)Se by a chalcogenizationprocess where the Cu(In,Ga) film is both selenized and sulfurized,meaning the final absorber (CIGSSe) contains both selenium and sulfur.Unfortunately, CIG(S)Se formed using a 2-step process has not yetachieved >20% efficiency, and lags ˜2% behind the laboratory champion ofCIGSe. This is mainly due to the fact that it is challenging to controlboth bandgap grading and maintain a high minority carrier lifetime whensulfur is introduced.

Unfortunately, the traditional 2-step approach based on Cu(In,Ga)followed by selenization (without introducing sulfur) has so far onlyresulted in flat bandgap profiles, or single-graded CIGSe, resulting inefficiencies <16.0%.

It should be noted that the above cited efficiencies are laboratorychampion efficiencies for ˜0.5 cm² solar cells, not to be confused withcommercially available, average, solar panel efficiencies which aretypically 5-6% lower than laboratory champions, due to a combination ofnon-uniformity within solar cells, mismatch between series-connectedcells, absorption losses in thick TCO layers, encapsulant, and glass,scribe and edge losses, and additional series resistance, all inaddition to running a different process in the factory compared to thelaboratory.

One of the main challenges for 2-step selenization is to control thephase separation in the Cu-poor film. High efficiency CIG(S)Se requiresa Cu-poor (p-type) CIGSe film. Cu-poor Cu(In,Ga) metal films prior tochalcogenization are multi-phasic (2 or more separate phases present inthe film), and as such, are hard to deposit in a homogeneous fashionthat provides a conformal, smooth, uniform Cu(In,Ga) film, especially,due to the fact that indium-rich phases have the tendency to agglomeratedue to poor wetting of underlying surfaces. Laterally uniform Cu(In,Ga)and Cu(In,Ga)Se₂ films are needed to avoid the formation of weak diodesthat reduce the overall solar cell efficiency.

The agglomeration of indium is typically minimized by reducing thedynamic deposition rate, and/or controlling the substrate temperatureduring PVD, and/or introducing a multi-layer stack of alternating layersof In-rich and Cu-rich layers, all resulting in additional CapitalExpenditure (CapEx). Other approaches try to avoid the phase separationby depositing a chalcogenide precursor film by PVD from binary, ormultinary chalcogenide targets which results in a CapEx investmenttypically >3× higher than for PVD-CIG due to the deposition of a film˜3× thicker with a lower dynamic deposition rate. In addition, directmaterial costs for the chalcogenide targets are higher than for themetallic targets.

A second challenge for 2-step selenization is to control bandgap gradingin depth in the final CIGSe film by Ga/(In+Ga) compositional grading.Ga-rich phases selenize slower than Cu and In, and therefore, most ofthe Ga collects at the back of the CIGSe film resulting in asingle-graded CIGSe film. One way to avoid this Ga migration andmaintain a flat Ga distribution is to extend the selenization time (>30min), and go to high temperatures (550-600C), not compatible with alllow-temperature, low-cost substrates. Furthermore, this has not resultedin any double-graded CIGSe (>20%).

A third challenge for 2-step selenization is to prevent adhesion failureof the CIGSe film due to stress resulting from the expansion fromCu(In,Ga) to CIGSe at elevated temperature. The expansion from the metalfilm to the chalcogenide film can be 2.5-3.0× in volume. Additionally,the overall stack of layers may have very different coefficients ofthermal expansion, thickness, and Young's modulus.

A second way of grading CIGS materials is by a 4-step approach asillustrated in FIG. 7. In step 702, “metal precursor” films aredeposited. For CIGS-like absorbers, the metal precursor films compriseGroup IB and Group-IIIA metals. In the case of CIGS absorbers, themetals comprise Cu, In, and Ga, with/without a Na source. This metalprecursor film needs to be converted to a chalcogenide to form theabsorber layer. The metal precursor film is converted (partially orfully) to a chalcogenide by heating the film in the presence of a sourceof one or more Group-VIA elements as indicated in step 704. As usedherein, it will be understood that “partially converted” will beunderstood to mean that at least a portion of the metal precursor filmis converted to a chalcogenide through exposure to a chalcogen atelevated temperature. In step 706, a layer rich in a bandgap-increasingmetal (relative to the metal precursor film deposited in step 702) isformed on the surface of the partially or fully chalcogenized precursorfilm. For example, if the metal precursor film deposited in step 702 isa Cu—In—Ga material, then at least one of Ga/(Ga+In) or Ag/(Ag+Cu) isgreater in the layer deposited in step 706 than in the metal precursorfilm deposited in step 702. In step 706, the layer rich in abandgap-increasing metal may be a metal, a metal alloy, or a metalchalcogenide material (e.g. metal oxide, metal sulfide, metal selenide,metal telluride, etc.). In step 708, the entire precursor stack to formthe final absorber is converted using a chalcogenization process. Thechalcogenization process may include an additional anneal step at theend to improve the device performance as illustrated in step 710.Details of a chalcogenization process including an additional annealstep are described in U.S. patent application Ser. No. 13/283,225,entitled “Method of Fabricating CIGS by Selenization at HighTemperatures”, filed on Oct. 27, 2011, which is herein incorporated byreference.

Generally, the 4-step method may comprise more than 4 steps when variouswet chemical and/or conversion methods (e.g. for densification orcontaminant removal) and/or deposition steps are used to form the metalprecursor film and/or the metal rich layer. As discussed above, themetal precursor film and/or the metal rich layer may each be a singlelayer or may each be formed from multiple layers, it may be dense orporous.

In each of the multi-step methods described above and the examples to bedisclosed below, a metal precursor film(s) is deposited. Typically, theprecursor material will deviate in shape, size, composition,homogeneity, crystallinity, or some combination of these parameters fromthe absorber material that is ultimately formed as a result of themethod. As mentioned previously, the metal precursor film(s) cancomprise multiple layers. These layers may be deposited by the same orby different deposition techniques. These layers can be porous, ordense.

The metal precursor film(s) can be deposited using a number oftechniques. Examples comprise dry deposition techniques such as batch orin-line (co)evaporation, batch or in-line PVD (sputtering), ALD, CVD,Plasma enhanced CVD (PECVD), Plasma enhanced ALD (PEALD), atmosphericpressure CVD (APCVD), ultra-fast atmospheric ALD, etc.

The efficiency of a TFPV device depends on the bandgap of the absorbermaterial. The goal is to have the bandgap tuned to the energy range ofthe photons incident on the device. The theoretical upper limit for asingle p-n junction solar cell has been calculated to be about 33 to34%. The peak in the efficiency occurs for values of the bandgap betweenabout 1.0 eV and about 1.5 eV, and more specifically between about 1.3eV and about 1.5 eV. The bandgap for CIGSe films varies smoothly fromCISe=1.00 (i.e. Ga/(Ga+In)=0.0) to CGSe=1.68 (i.e. Ga/(Ga+In)=1.0). Theregion of interest is from Ga/(Ga+In)=0.4 (˜1.23 eV) to Ga/(Ga+In)=0.7(˜1.45 eV).

Another problem typically encountered during selenization is thedifficulty to control the degree of selenization at higher temperatures.The selenization reaction of CIGSe occurs at temperatures above about350 if the Se source is H₂Se. In an exemplary batch furnace, the ramprates are generally limited to about 10C/min by hardware. Those skilledin the art will understand that parameters such as ramp rates andtemperature uniformity within processing equipment depend on the detailsof the equipment and that exemplary values used herein are not limiting.If the furnace temperature is increased to 600C, delamination at theMo/CIGSe interface is observed due to over-selenization and formation ofa thick MoSe₂ layer. In some embodiments of the present invention, afast gas exchange step is introduced at the high temperature step toreplace H₂Se in the furnace with an inert gas such as Ar, N₂, etc. tostop further selenization. This resolves the delamination problem due toover-selenization by limiting the formation of the MoSe₂ layer. Detailsof the fast gas exchange process are described in U.S. patentapplication Ser. No. 13/283,225 entitled “Method of Fabricating CIGS bySelenization at High Temperature” filed on Oct. 27, 2011 and is hereinincorporated by reference.

FIG. 8 illustrates a diagram depicting the temperature, temperatureuniformity, gas flows, and chamber pressure during an exemplaryselenization/sulfurization process. Details of the selenization processare described in U.S. patent application Ser. No. 13/461,495 entitled“Method of Uniform Selenization and Sulfurization in a Tube Furnace”filed on May 1, 2012 and is herein incorporated by reference for allpurposes. Those skilled in the art will understand that parameters suchas flow rates, gas composition, ramp rates, and temperature uniformitywithin processing equipment depend on the details of the equipment andthat exemplary values used in the discussion to follow are not limiting.The Cu—In—Ga precursor film may be a blanket film covering the entiresubstrate or may comprise a plurality of site isolated regions whereinthe composition of the Cu—In—Ga precursor film has been varied in acombinatorial manner as discussed previously. The uniformity of theselenization/sulfurization process is largely determined by thetemperature uniformity within the furnace. The temperaturenon-uniformity between the shelves in the furnace is illustrated by thecurve labeled “Delta(TC_shelf1−TC_shelf3)”. It is noted that thenon-uniformity is large during temperature ramp steps from onetemperature to the next temperature. If the precursor film is exposed toa source of Se during these periods, the selenization of the film wouldbe non-uniform and the device performance would be poor. Thisnon-uniformity may be addressed by limiting the exposure to a source ofSe during periods of high temperature non-uniformity and by adjustingthe ramp rate of the furnace to maintain a temperature non-uniformityacross the substrate of less than about 100. However, in the absence ofa source of Se, indium will diffuse and agglomerate. In someembodiments, the precursor film is exposed to an inert gas flow (i.e.Ar) during the temperature ramp steps, denoted by time period 801 inFIG. 8. To decrease the indium agglomeration, the pressure within thefurnace is increased to between about 1 atmosphere and about 2atmospheres during temperature ramp steps. A pressure of 1 atmospherehas been illustrated in FIG. 8. The target temperature range for timeperiod 801 is between about 350C and about 450C, and preferably betweenabout 400C and about 450C. The temperature setpoint in FIG. 8 for timeperiod 801 has been illustrated as 400C.

Once the temperature has stabilized, the pressure in the furnace isreduced to between about 600 Torr and 700 Torr and the precursor film isexposed to a source of Se (e.g. H₂Se, diethylselenide (DESe), Se vapor,etc.). In this case, the source of Se is H₂Se, denoted by time period802 in FIG. 8. An exemplary concentration of the H₂Se is about 1 molar %H₂Se in Ar. The temperature uniformity within the furnace is acceptableduring this step and the selenization/sulfurization process will also beuniform.

As illustrated in FIG. 8, the furnace is then ramped to an intermediatetemperature of between about 450C and about 550C, denoted by time period803 in FIG. 8. The temperature setpoint in FIG. 8 for time period 803has been illustrated as 500C. As before, during this time, the CIGS filmis not exposed to a source of Se. The furnace is filled with an inertgas (i.e. Ar) and the pressure within the furnace is increased tobetween about 1 atmosphere and about 2 atmospheres during temperatureramp steps. A pressure of 1 atmosphere has been illustrated in FIG. 8.

In some embodiments, it is advantageous to expose the CIGS film to asecond selenization/sulfurization process, denoted by time period 804 inFIG. 8. This step completes the selenization/sulfurization of the film.As before, the pressure in the furnace is reduced to between about 600Torr and 700 Torr and the precursor film is exposed to a source of Se(e.g. H₂Se, diethylselenide (DESe), Se vapor, etc.). In this case, thesource of Se is H₂Se. The higher temperature results in increasedcrystallinity, larger grains, and improved optoelectronic performance.To prevent the over-selenization of the film, a fast gas exchange stepis introduced near the beginning of the high temperature step. In thisprocess, the H₂Se flow is stopped and the H₂Se gas within the chamber isquickly removed through a combination of an increased inert gas purgeand pumping capacity.

As illustrated in FIG. 8, the furnace is then ramped to a finaltemperature of between about 550C and about 650C to anneal the film,denoted by time period 805 in FIG. 8. As before, during this time, theCIGS film is not exposed to a source of Se. The furnace is filled withan inert gas (i.e. Ar) and the pressure within the furnace is increasedto between about 1 atmosphere and about 2 atmospheres during temperatureramp steps. A pressure of 1 atmosphere has been illustrated in FIG. 8.The purpose of this anneal step is mainly to allow the indium andgallium to interdiffuse within the film.

In some embodiments, it is advantageous to expose the CIGS film to anoptional sulfurization process, denoted by time period 806 in FIG. 8.This step completes the sulfurization of the film. As before, thepressure in the furnace is reduced to about 600 Torr and the precursorfilm is exposed to a source of S. In this case, the source of S is H₂S.

In some embodiments of the present invention, the methods areimplemented on a rapid thermal processing (RTP) system configuration. Inan RTP system, the temperature of the substrates is increased andcontrolled through the use of lamp heaters while the substrates residein a process chamber. The chambers may operate at pressures aboveatmospheric pressure or may operate at pressures below atmosphericpressure.

In some embodiments of the present invention, substrates are loaded intoa RTP chamber that raises the temperature of the substrate from aboutroom temperature to between about 350C and about 450C, and preferably tobetween about 400C and about 450C, in the presence of Ar at a pressurebetween about 1 atmosphere and about 2 atmospheres. After reaching thedesired temperature, the substrates are held at that temperature untilthe substrates reach thermal equilibrium. The slow ramp and soak at lowtemperature ensures that the substrate and the deposited Cu—In—Ga metalprecursor film do not suffer from thermal shock and that the temperatureis uniform. In the next step, the precursor film is exposed to about 1molar % H₂Se in Ar at a pressure of less than 1 atmosphere and theCu—In—Ga metal precursor film is partially selenized for a period oftime. This step secures the indium in a selenized state and helps toprevent agglomeration. In the next step, the temperature is raised tobetween about 500C and about 550C and the Cu—In—Ga metal precursor filmselenized for a period of time. The higher temperature is possible dueto the earlier reaction of the In with the H₂Se during the initial lowtemperature partial selenization step. The higher temperature results inincreased crystallinity, larger grains, and improved optoelectronicperformance. To prevent the over-selenization of the film, a fast gasexchange step is introduced near the beginning of the high temperaturestep. In this process, the H₂Se flow is stopped and the H₂Se gas withinthe chamber is quickly removed through a combination of an increasedinert gas purge and pumping capacity. The CIGS film can be annealed atbetween about 550C and about 650C to influence the Ga distributionthroughout the depth of the film.

In some embodiments, it is advantageous to expose the CIGS film to anoptional sulfurization process. This step completes the sulfurization ofthe film. As before, the pressure in the RTP is reduced and theprecursor film is exposed to a source of S. In this case, the source ofS can be H₂S.

An alternate furnace profile is illustrated in FIG. 9. As discussedpreviously, a fast gas exchange step is introduced to replace H₂Se inthe furnace with an inert gas such as Ar, N₂, etc. to control theselenization. A detailed discussion of this furnace profile is describedin co-owned U.S. patent application Ser. No. 13/563,448 entitled “Methodof Chalcogenization to Form high Quality CIGS for Solar CellApplications” which is herein incorporated by reference for allpurposes.

FIG. 9 illustrates a diagram depicting the temperature, gas flows, andchamber pressure during a selenization process according to someembodiments of the present invention. The Cu—In—Ga metal precursor filmmay be a blanket film covering the entire substrate or may comprise aplurality of site isolated regions wherein the composition of theCu—In—Ga metal precursor film has been varied in a combinatorial manneras discussed previously. The uniformity of the selenization process islargely determined by the temperature uniformity within the furnace. Ifthe precursor film is exposed to a source of Se during these periods,the selenization of the film would be non-uniform and the deviceperformance would be poor. This non-uniformity may be addressed byeliminating the exposure to a source of Se during these periods.However, in the absence of an exposure to a source of Se, indium willdiffuse and agglomerate at temperatures above about 350C. In someembodiments, the precursor film is exposed to an inert gas flow (i.e.Ar) with a small amount of H₂Se during the initial temperature rampsteps, denoted by time period 901 in FIG. 9. As an example, the flow ofa molar 1% H₂Se in Ar gas may be held at about 1 standard liter perminute (slpm) during the initial temperature ramp. This provides enoughSe to prevent the agglomeration of In, but does not provide enough Se topromote non-uniform selenization due to the temperature non-uniformity.A pressure of less than 1 atmosphere has been illustrated in FIG. 9.This pressure is selected as a safety precaution due to the toxic natureof H₂Se. The target temperature range for time period 901 is betweenabout 300C and about 400C. As discussed previously, those skilled in theart will understand that parameters such as flow rates, gas composition,ramp rates, and temperature uniformity within processing equipmentdepend on the details of the equipment and that exemplary values used inthe discussion to follow are not limiting.

Once the temperature has stabilized, the metal precursor film is held atthis temperature and exposed to a dilute source of Se (e.g. H₂Se,diethylselenide (DESe), Se vapor, etc.). In this case, the source of Seis H₂Se, denoted by time period 902 in FIG. 9. An exemplaryconcentration of the H₂Se is about 1 molar % H₂Se in Ar. Theconcentration of Se is low so that the selenization process is slow anduniform. The temperature uniformity within the furnace is acceptableduring this step and the partial selenization process will also beuniform.

As illustrated in FIG. 9, the furnace is then ramped to an intermediatetemperature of between about 400C and about 550C, denoted by time period903 in FIG. 9. As before, during this time, the CIGS film is exposed toa dilute source of Se. The furnace is filled with an inert gas (i.e. Ar)and the pressure within the furnace is increased to between about 1atmosphere and about 2 atmospheres during temperature ramp steps. Apressure of 1 atmosphere has been illustrated in FIG. 9. This stepcompletes the selenization of the metal precursor film. The increasedtemperature serves to increase the kinetics of the selenization reactionand the metal precursor film is fully converted.

As illustrated in FIG. 9, the furnace is then ramped to a finaltemperature of between about 550C and about 650C to anneal the film,denoted by time period 905 in FIG. 9. During this time period, the CIGSfilm is not exposed to a source of Se. The furnace is filled with aninert gas (i.e. Ar) and the pressure within the furnace is increased tobetween about 1 atmosphere and about 2 atmospheres during temperatureramp steps. A pressure of 1 atmosphere has been illustrated in FIG. 9.The purpose of this anneal step is mainly to allow the indium andgallium to interdiffuse within the film.

In each of the multi-step methods described herein, the performance ofthe absorber layer can be improved by incorporating a small amount (i.e.about 0.1 atomic %) of Na prior, during, or after the growth of theabsorber layer. The incorporation of Na results in improved filmmorphology, higher conductivity, and beneficial changes in the defectdistribution within the absorber material. The Na may be introduced in anumber of ways. The Na may diffuse out of the glass substrate, out of alayer disposed between the glass substrate and the back contact (e.g. aNa containing sol-gel layer formed under the back contact), or out ofthe back contact (e.g. molybdenum doped with a Na salt). The Na may beintroduced from a separate Na containing layer formed on top of the backcontact. The Na may be introduced by incorporating a Na source in theCu(In, Ga) precursor film. Examples of suitable Na sources compriseNa₂Se, Na₂O₂, NaF, Na₂S, etc. The Na may be introduced from a separateNa containing layer formed on top of the Cu(In, Ga) precursor film. TheNa may be introduced from a separate Na containing layer formed on topof the partially or completely chalcogenized CIGS film. The Na may beintroduced by incorporating a Na source in the Ga-rich film. The Na maybe introduced from a separate Na containing layer formed on top of theGa-rich film. The Na may be introduced after the final selenizationstep, followed by a heat treatment. The Na may be introduced bycombining any of these methods as required to improve the performance ofthe absorber layer. It should be noted that similar Group IA, and/orGroup IIA elements like K, and Ca might be used instead of sodium.

In some embodiments, the Na may be introduced as a NaF layer formedusing a CVD technique in the selenization equipment. FIG. 10 provides aflow chart that describes methods associated with these embodiments. Instep 1002, a multi-component metal precursor film (e.g. Cu, In, Ga) isdeposited on a substrate as discussed previously. As discussedpreviously, the metal precursor film may also include Ag. As discussedpreviously, a portion of the metal precursor film may be partiallychalcogenized.

In step 1004, the substrate and the multi-component metal precursor filmare inserted into the selenization equipment. Examples of suitableselenization equipment include the batch furnaces discussed previouslywith respect to FIGS. 8 and 9, in-line systems, or RTP systems.

In step 1006, a NaF layer is deposited on the surface of themulti-component metal precursor film before the first step (e.g. 801 and901) of the chalcogenization process (i.e. selenization). The batchfurnace configuration is well suited for the deposition of the NaF layerusing CVD techniques. The NaF layer can be deposited at temperaturesbetween about 150C and 350C. The NaF layer can be deposited at pressuresbetween about 0.1 torr and 800 Torr. Alternatively, the NaF layer can bedeposited in an in-line CVD system. Alternatively, the NaF layer can bedeposited in an RTP system. Examples of precursors that are suitable forthe deposition of the NaF layer using CVD include sodiumhexafluoro-iso-propoxide, sodium perfluoro-t-butoxide, sodiumhexafluoroacetylacetonate, and sodium heptafluoro-octadionate. Thethickness of the NaF layer is typically between 5 nm and 100 nm.

In step 1008, the entire precursor stack to form the final absorber isconverted using a chalcogenization process. The chalcogenization processmay include an additional anneal step at the end to improve the deviceperformance as illustrated in step 1010.

In some embodiments, the Na may be introduced using a Na CVD precursorin the selenization equipment. FIG. 11 provides a flow chart thatdescribes methods associated with these embodiments. In step 1102, amulti-component metal precursor film (e.g. Cu, In, Ga) is deposited on asubstrate as discussed previously. As discussed previously, the metalprecursor film may also include Ag. As discussed previously, a portionof the metal precursor film may be partially chalcogenized.

In step 1104, the substrate and the multi-component metal precursor filmare inserted into the selenization equipment. Examples of suitableselenization equipment include the batch furnaces discussed previouslywith respect to FIGS. 8 and 9, or in-line systems.

In step 1106, a Na precursor is introduced during the chalcogen exposuresteps as discussed previously (e.g. 802 and 902) of the chalcogenizationprocess (i.e. selenization). The batch furnace configuration is wellsuited for the use of Na precursors. The Na precursor exposure can occurat temperatures between about 150C and 350C. The Na precursor exposurecan occur at pressures between about 0.1 torr and 800 Torr.Alternatively, the Na precursor exposure can occur in an in-line CVDsystem. Examples of Na precursors that are suitable for the exposureinclude sodium hexafluoro-iso-propoxide, sodium perfluoro-t-butoxide,sodium hexafluoroacetylacetonate, and sodium heptafluoro-octadionate.During step 1106, the entire film is also converted to a chalcogenide.The chalcogenization process may include an additional anneal step atthe end to improve the device performance as illustrated in step 1108.

The deposition of the NaF layer in the selenization equipment allows theconcentration and uniformity of the Na to be tightly controlled.Additionally, the deposition of the NaF layer in the selenizationequipment eliminates the need for the dedicated equipment typically usedto introduce the Na. Examples of equipment that may be eliminatedinclude e-beam or thermal evaporators, sol-gel coating and curingsystems, specialized metal sputtering targets that incorporate Na salts,etc. Overall, this reduces the complexity and the cost associated withthe manufacture of the TFPV devices. An illustrative example of thebenefits of Na on the efficiency of CIGS absorbers is discussed below.The NaF layers in the example were formed by e-beam evaporation.However, the NaF layer could also be deposited using the CVD techniquesdiscussed previously.

ILLUSTRATIVE EXAMPLES Cited References are Listed at the End

These examples discuss a sodium fluoride (NaF) thickness variation studyfor the H₂Se batch furnace selenization of sputtered Cu(In, Ga) films ina wide range of Cu(In, Ga) film compositions to form CIGSe films andsolar cells. Literature review indicates a lack of consensus on themechanisms involved in Na altering CIGSe film properties. In this work,for sputtered and batch-selenized CIGSe, NaF addition results in reducedgallium content and an increase in grain size for the top portion of theCIGSe film, as observed by scanning electron microscopy, secondary ionmass spectrometry, and extraction of the band gap from external quantumefficiency and photoluminescence data. The addition of up to 20 nm ofNaF resulted in improvement in all relevant device parameters:efficiency, open-circuit voltage, short-circuit current, and fillfactor. The best results were found for 15 nm NaF addition, resulting insolar cells with 16.0% active-area efficiency (without anti-reflectivecoating) at open-circuit voltage (V_(OC)) of 674 mV.

INTRODUCTION

Cu(In, Ga)Se₂ (CIGSe or CIGS) has proven to be a prime candidate forhigh-efficiency thin-film photovoltaics (TFPV) with laboratory championefficiencies over 20% [1, 2], and panels from manufacturing linesproducing champions in the range of 13-15%. During the past decade,global accumulated nameplate manufacturing capacity of CIGSe-based solarcells has reached the 1-2 GW range.

CIGSe films have been grown over the past decades by a number ofdifferent vacuum deposition techniques including co-evaporation [3, 4],selenization and sulfurization of sputtered Cu(In, Ga) [5], reactivesputtering of metallic targets [6], (non-) reactive sputtering ofchalcogenide targets [7], and various non-vacuum techniques [8]. MostCIGS TFPV manufacturing capacity today relies on batch furnaceselenization and sulfurization with hydride gases (H₂Se/H₂S) ofsputtered Cu(In, Ga). During the remainder of this discussion CIGSe willbe used as a label to describe all common alloys, like CIGSe, CIGSSe,CISe, and CISSe.

It is well known that the control of sodium (Na) during the growth ofthe CIGSe absorber layer is crucial to achieve high efficiency [4, 9,10]. Several extensive reviews on the influence of Na exist [11-15]mainly dealing with co-evaporated CIGSe.

The growth path to the final CIGSe film can vary tremendously betweenthe “bottom-up” co-evaporation and “top-down” selenization of metallicCu(In, Ga), or even within the same growth method for varying processingconditions. This makes it challenging to transfer learning fromco-evaporated CIGSe to CIGSe grown by batch selenization. Whilesputtered Cu(In, Ga) followed by H₂Se/H₂S batch-selenization is the mostcommon CIGSe technology on the manufacturing floor today, there are farfewer reports on the effects of Na in such films compared to the numberof studies reported for co-evaporation. In addition, it is still unclearhow to best select the optimal Na location and source, especially whentrying to introduce Na uniformly over large areas.

This discussion presents a detailed CIGSe film and solar cellinvestigation for sputtered Cu(In, Ga) followed by H₂Se batchselenization with active Na addition for varying NaF thicknesses, in abroad range of Cu/(In+Ga) [CGI], Ga/(In+Ga) [GGI], and Cu(In,Ga)thicknesses enabled by a combinatorial high-throughput method. BothCIGSe film and related device properties are characterized, and resultsare compared with previous work. We find that NaF addition results inreduced gallium content and an increase in grain size for the topportion of the CIGSe film, and an improvement in all relevant deviceparameters.

Sodium Influence on CIGS Films and Solar Cells

So far, 20% efficiencies have only been reported by relying on Nadiffusion from soda lime glass (SLG, or standard “float glass”) duringco-evaporation of CIGSe at processing temperatures reaching 550-600° C.[1, 2, 16]. Efficiencies up to 18.7% on plastic [18] have been reportedwith adding NaF.

Na has been reported to alter many film and device properties forco-evaporated CIGSe. It slows down the indium-gallium inter-diffusionduring 3-stage co-evaporation [19-22], slows down inter-diffusion in astack of CGSe/CISe as explained by a reduced number of vacancies in thepresence of Na [23], and slows down Cu in-diffusion at low temperatures(<450° C.) [24]. Rockett observed that Na reduces the diffusivity of Gaout of GaAs into CI(G)Se [15].

Na has been reported to alter crystal orientation for (2- and 3-stage)co-evaporation by inducing the (112) orientation over the (220, 204)orientation when present during CIGSe growth, albeit dependent on thecombination of Na addition and CIGSe growth methods [17, 19]. NREL'schampion cells exhibit a preferred crystal orientation of (220, 204) not(112) [1].

The grain size of co-evaporated CIGSe has been reported as beingunaffected by Na for grain sizes up to 500 nm [30], but also to bothincrease from below 0.5 μm up to 1.0 μm size for 2-stage co-evaporatedCIGSe [17], and decrease for 3-stage co-evaporated CIGSe from 1-2 μmdown to below 0.5 μm upon the addition of Na [19, 21, 22, 31]. Theincrease in grain size for 2-stage co-evaporated CIGSe by Na implies analteration in nucleation or enhanced atomic diffusivity, especially ongrain surfaces where growth occurs [15].

The selenization of the Mo electrode is enhanced by the presence of Na[22, 46], where sodium selenide compounds might play a role in thisprocess [47].

The co-evaporated CIGSe TFPV devices grown in the presence of Na mostcommonly show higher efficiencies, due to higher open-circuit voltage(V_(OC)), and higher fill factor (FF) [11-15]. The increase in V_(OC)(and FF) is believed to be caused by increased net carrierconcentration, typically one order of magnitude [20, 31] due to eitheran increased p-type doping concentration with a shorter resulting SpaceCharge Region (SCR), potentially by a reduction of compensating donors,and/or reduced recombination.

There are far fewer reports on the effects of Na in sputtered Cu(In, Ga)films followed by H₂Se/H₂S batch selenization compared to the number ofstudies reported for co-evaporation. Wieting et al. showed theimportance of separate Na addition for sputtered Cu(In, Ga) followed byH₂Se/H₂S batch conversion [55]. A steady increase of efficiency with Nadosing was observed as a result of an increase in all three mainparameters (V_(OC), J_(SC), and FF), accompanied by an improvement invisual uniformity.

A technology related to the hours-long H₂Se/H₂S batch selenization isthe deposition of elemental selenium on top of Cu(In, Ga) followed byrapid thermal processing (RTP), typically for less than 15 min. Probstet al. describe an increase in efficiency from 5-6% to 9-13% accompaniedby an increase in grain size for RTP-grown CIGSe when evaporating sodiumselenide between the Mo and the Cu(In, Ga) [56]. The separate Naaddition for RTP-grown CIGSe allows for improved uniformity—as observedin optical beam induced current (OBIC) mapping and reproducibility—andhence higher efficiencies [57], the latter at least partially due to anincrease in the free carrier concentration [58].

Na is shown to alter the intermediate phase formation and consumptionfor RTP-grown CIGSe, and therefore affects the final grain-sizedistribution, homogeneity, and compositional depth profile of thedesired quarternary Cu(In, Ga)Se₂ film in a negative way [59, 60]. Thisnegative effect of Na is anticipated to hold mainly for solid-statereactions based on (non-redox reaction) inter-diffusion. Theseconsiderations are supported by the effective heat of formation model inwhich Na is present as sodium polyselenides at the crystallite surfaces[51].

Determining what mechanisms allow Na to have such a huge influence onthe CIGSe growth, and CIGSe thin film device properties is of interest.Various studies propose that Na acts at the growing surface [15, 47,51]. The primary effect of Na is proposed to be the organization of thepoint defects during growth, thereby providing an improved crystalstructure. The related increase in net hole densities has been proposedto arise mainly from a reduction of compensating In_(Cu) anti-sitedonors [13, 42, 52]. In addition, first-principles calculations showthat Na suppresses the ordered defect compound formation [13]. Theaction of Na at the growing surface has been proposed to occur viasodium selenides acting as a desirable Se-reservoir [47], or negativelyinfluence the thermodynamics and kinetics of RTP-grown CIGSe [51].Furthermore, the presence of Na might result in a redistribution ofoxygen in the CIGSe film [13, 37].

Kronik et al. have proposed a grain boundary passivation model toexplain the increase in hole density: Na catalyzes the oxygenation ofdangling In bonds in the grain boundaries resulting in a reduction ofcompensating donors [14, 53]. Rudmann et al. hypothesize that Napassivates the donors at grain boundaries more than it alters CIGSegrowth kinetics, derived from the positive effect of a post-depositiontreatment with NaF for 3-stage co-evaporated CIGSe grown at lowtemperatures (<450° C.) [31]. A similar (though higher temperature) posttreatment on epitaxial CIGSe showed a similar beneficial reduction incompensating donor density [15, 42].

In summary, Na has been observed to alter both the path (kinetics)towards and the preferred final state (thermodynamics) of the CIGSefilm, in addition to the sensitivity of the CIGSe film to theatmosphere. Furthermore, the partial conversion of the Mo filmunderneath the CIGSe film is altered by the presence of Na as well. Themost striking is the observation of both positive and negative effectson CIGSe film formation.

EXPERIMENTAL

The Mo-coated soda lime glass substrates were purchased from acommercial vendor (Guardian Industries). The substrates were cut into13.0 cm by 6.5 cm rectangles and cleaned with detergent solution, thenblown dry with N₂ prior to precursor deposition. For experiments withcontrolled NaF addition we used substrates with an alkali diffusionbarrier (SiO_(x)N_(y)), otherwise substrates without SiO_(x)N_(y) wereused.

The Cu(In, Ga) precursors were deposited in an Intermolecular Tempus™P-30 High Productivity Combinatorial (HPC™) sputtering tool that allowsfor the simultaneous use of 4 different targets for co- and/orsequential-sputtering of Cu, In, and Ga with systematically controlledlateral gradients in composition and thickness within one substrate. Theranges of film thickness and composition could be accurately controlledby PVD modeling. The film thickness range was 450-600 nm withcomposition range of Cu/(In+Ga)=0.8-1.0, and Ga/(Ga+In)=0.30-0.45.Plates were stored after Cu(In, Ga) deposition in a N₂-containingglovebox for several days prior to selenization. NaF is deposited byelectron beam evaporation, either on the Mo back contact, or on top ofthe Cu(In, Ga) prior to selenization. As discussed previously, the NaFcould have been deposited using a CVD technique in the selenizationequipment. The NaF thickness was varied from 10 to 30 nm. Selenizationof the Cu(In, Ga) metal precursors with H₂Se/Ar was performed in acommercial quartz furnace customized for safety. The selenizationprocess includes two soak steps in H₂Se at 250° C. followed by 500° C.,finalized with an in-situ Ar annealing at 600° C.

The complete solar cells included a buffer layer of ˜50 nm CdS depositedby chemical bath deposition (CBD) in a beaker, followed by a doublelayer (high resistivity/low resistivity) of (pulsed) DC sputtered ZnO:Alin a commercial PVD sputtering tool. The thickness of the i-ZnO andZnO:Al layers were about 50 nm and 500 nm, respectively. The resistivityof the ZnO:Al film was 1.4×10⁻³ Ωcm. Ni/Al front contacts were depositedin an electron beam evaporator through a shadow mask.

The thickness of the Ni and Al layers were 50 nm and 3 μm, respectively.Back contact was formed by In soldering on exposed Mo after mechanicalremoval of the top layers. No anti-reflection coatings were used. Thefinished cells were about 0.5 cm by 1.0 cm and all cell parameters arereported for a nominal active-area of 0.44 cm². Precise cell area andgrid shadow area were determined by image analysis of the champion cellsusing a high resolution camera. No devices were made with 30 nm NaF dueto peeling during CdS deposition.

The structure of the CIGSe absorber was investigated by X-raydiffraction (XRD) with Cu K_(a) radiation. Surface morphology and grainsize were observed by scanning electron microscopy (SEM). At least 5images at different locations per sample for a select group of sampleswere made to ensure statistical significance of the images shown. Thecomposition was determined by X-ray fluorescence (XRF). All CGI, GGI,and Cu(In,Ga) thickness values are calculated based on XRF after Cu(In,Ga) deposition. Se percentage values are calculated based on XRF afterselenization. Compositional depth profile was determined by SecondaryIon Mass Spectrometry (SIMS) using Cs⁺ primary beam in positivedetection mode. Optoelectronic quality and surface band gap wasinvestigated by spectrally resolved room temperature photoluminescence(PL), using a 660 nm solid state laser with a spot size ˜1 mm indiameter. The presented SIMS and XRF measurements are performed on bareCIGSe witness films. Numerous other samples were measured (not shown)after etching the full solar cell down to CIGSe. SEM and XRDmeasurements were performed on CIGSe films after removing the CdS, TCO,and grid using an acidic solution. SIMS, XRD, and SEM was performed at asimilar location on the 13.0 cm by 6.5 cm rectangles with CGI=0.85, andGGI=0.35. PL was performed on full cells.

Current-Voltage (J-V) measurements were performed in a Newport OrielSolar Simulator automated by Intermolecular for fast J-V measurements onmultiple cells. Test condition was simulated air mass 1.5 global(AM1.5G, 100 mW/cm²) at room temperature. The J-V parameters wereextracted using an analytical method [62]. The inverse of the slope atJ_(sc) was used for the shunt resistance. QE was measured on an Orielmodel IQE-200 with a 1 mm×2.5 mm rectangular spot size from a quartztungsten halogen lamp and monochromator with chopper running at 30 Hz.The External Quantum Efficiency (EQE) metrology system was automated byIntermolecular for fast measurements on multiple cells.Capacitance-Voltage (C-V) measurements were performed on Agilent modelB1500 to measure the carrier density. The C-V measurements wereperformed at a similar location on the 13.0 cm by 6.5 cm rectangles withCGI=0.85, and GGI=0.35.

Each 13.0 cm by 6.5 cm rectangle hosts 110 unique solar cells due to thesystematic lateral variation in the Cu(In,Ga) film. The results beloware a selection of the more than 6,000 unique solar cells made duringthis study to ensure statistical significance of the results.

Results and Discussion

Variation in the CIGSe Film Microstructure with Varying NaF LayerThickness

Cross-sectional and plan-view SEM imaging (see FIG. 12) is used toinvestigate the effects of Na on the microstructure of the CIGSe layerfor NaF addition on top of Cu(In, Ga). For a NaF thickness from 0 nmthrough 10 nm, top-down SEM images show signs of potential (binary)impurity phases, whereas this is less observed for 15 nm and 20 nm, andnot seen for 30 nm. A clear increase in grain size and reduced roughnesscan be observed with increasing NaF thickness. Furthermore, the grainsize for the no-barrier CIGSe (FIG. 12 f) most resembles the grain sizeof the 10 nm NaF thickness.

Cross-sectional SEM images show the formation of a CIGSe bi-layer forall Na conditions investigated. A bottom layer of small grains withvoids is capped with a layer of large grains. The grain size of the toplayer increases with increasing NaF thickness. No signs of excessiveMoSe₂ formation can be found, however this does not exclude theformation of MoSe₂. The bi-layer formation has been observed previouslyfor CIGSe grown in a H₂Se/H₂S batch furnace [63], though differentgrain-size distributions can be obtained as well [64, 65].

Similar to previous work on RTP-grown CIGSe [51, 56] and for 2-stageco-evaporated CIGSe [17], an increase in grain size is observed with anincrease in Na though this is opposite to the grain size decreaseobserved for 3-stage co-evaporation [19, 21, 22, 31]. However, where aclear lateral bi-modal grain size distribution can be observed forRTP-grown CIGSe due to Na [51], this work only indicates a distinctbi-modal grain size distribution in depth for the H₂Se batch furnaceselenization.

Variation in the CIGSe Film Phase Purity with Varying NaF LayerThickness

FIG. 13 shows the XRD patterns of CIGSe films produced with differentNaF thicknesses. For all Na conditions, an asymmetry in the CIGSe peakswith a shoulder to the left is observed. The left shoulder has beenobserved previously, both for 3-stage co-evaporated CIGSe [19], andRTP-grown CIGSe [51] and is an indication of lack of homogeneity in GGI.The peak width is the largest for 30 nm NaF (FWHM=0.43), and thenarrowest for 0 nm NaF (FWHM=0.28). The diffraction intensity ratio of(112) peak to (220, 204) peak ranges from 3.0:1 (15 nm NaF) to 4.4:1 (30nm NaF) with no clear trend in NaF thickness. All CIGSe films show aslight preferred orientation in the (112) direction compared to JCPDSpowder standard of Cu(In_(0.7),Ga_(0.3))Se₂ (ratio 2.5:1).

Variation in the CIGSe Film Composition Depth Profile with Varying NaFLayer Thickness

FIG. 14 shows the Na, Ga, In, and Mo concentration depth profiles in theCIGSe films as measured by SIMS. GGI was calculated based on the ratioof the secondary ion counts. A clear increase in Na levels in the CIGSeand Mo film can be observed for the CIGSe films grown with additionalNaF compared to the CIGSe film grown on barrier-coated glass with 0 nmNaF. The Na concentration is the highest at the CIGSe surface and in theback of the CIGSe film near the Mo electrode, as commonly observed [12,31, 38]. The grain boundary area in the top layer decreases withincreasing NaF thickness, as can be observed in the cross-sectional SEMimages (FIG. 12). This might explain the lower Na concentration in thetop layer for 17.5 nm compared to 10 nm NaF. The high Na concentrationin the bottom layer of the CIGSe film might be solely due to the largesurface area of the small grains, though an increase in Na incorporationinto the CIGSe grain interior with an increase in GGI cannot be ruledout. Similarly, the formation of new Na-containing compounds, like (Na,Cu)(In, Ga)Se, or Na(In, Ga)Se might contribute as well [26, 45]. TheGGI depth profile shows a clear decrease in GGI homogeneity withincreasing NaF thickness. The increase in GGI at the CIGSe surfacecreating a notch is believed to be an artifact of the SIMS measurement,since it is not consistently observed.

Similar to the decrease in GGI homogeneity upon the addition of Na forRTP-grown CIGSe films [51], co-evaporated CIGSe [19-23], and epitaxialCIGSe [15], these SIMS data show a decrease in GGI homogeneity when Nais used during H₂Se batch selenization. It has been previously observedthat Na can also improve the GGI homogeneity in depth [66].

Na does not seem to influence the preferred crystal orientation for H₂Sebatch selenization, in contrast to observations made for co-evaporation[17, 19]. The combined observations in SEM and SIMS suggest that thesmall grains in the bottom portion of the CIGSe film are high in GGI. Areduction in grain size with an increase in GGI is commonly observed forco-evaporation [25]. This could also explain the increase in grain sizewith an increase in NaF for the top layer, due to the concomitantreduction in GGI in the top layer.

Variation in the CIGSe Solar Cell Performance with Varying NaF LayerThickness

Room temperature Capacitance-Voltage (C-V) measurements were taken at100 kHz in the dark for varying NaF thicknesses. FIG. 15 shows thecarrier concentration data as a function of NaF thickness for theselected cells. These measurements show an increase of oneorder-of-magnitude in majority carrier concentration when adding 10-20nm NaF compared to 0 nm NaF. Similar observations have been made uponthe addition of Na for both RTP-grown CIGSe [58] and co-evaporated CIGSe[20, 31].

FIG. 16 summarizes the device performance data for the best 20cells-per-plate selected for each NaF thickness. The next section ofthis discussion provides a detailed analysis of the device performancedata for all cells related to these plates.

FIG. 16 shows a clear jump in all four parameters (efficiency, V_(OC),J_(SC), and FF) from 0 nm to 10 nm NaF. Due to a significant drop inV_(OC) for 20 nm NaF, the efficiency peaks for 15 nm NaF. The changes inefficiency and FF with NaF addition most resemble the variation incarrier concentration from C-V measurements with NaF.

To get a better understanding of the interplay between Cu(In, Ga) filmcomposition and NaF thickness, FIGS. 17A-17C shows contour maps of GGI(by XRF) and NaF on CIGSe film and device parameters. The maps are onlypopulated for NaF thicknesses of 0, 10, 12.5, 15, 17.5, and 20 nm, whileGGI varies continuously for the range shown.

Due to the target configuration there is a dependence of CGI on GGIwithin one deposition (FIG. 17B). This means that both CGI and GGIincrease simultaneously. Also, the thicker Cu(In, Ga) films are made fora GGI in the range of 0.34 to 0.39. Despite the dependence of thicknessand CGI on GGI, the contour map shows a continuous decrease in Se % foran increase of GGI.

A prediction profiler analysis, as discussed later, examines theinfluence of the individual Cu(In, Ga) input parameters. The data usedin the maps and prediction profiler are filtered for efficiencies over5%.

Efficiency shows a clear dependence on GGI and NaF, with a maximum inthe region of GGI=0.38 and NaF=12-17 nm (FIG. 17A). The sudden cliff athigh GGI is attributed to too high CGI (impurity phase formation). Boththe FF and J_(sc) are mainly dictated by NaF, less by GGI, with the FFvery sensitive to NaF and maximum close to 15 nm NaF. V_(OC) is thehighest in the GGI=0.38 and NaF=20 nm area, yet this does not result inthe highest efficiency (15 nm).

The saturation current (not shown), ideality factor (not shown), andseries resistance contour maps (FIG. 17C) strongly resemble the inverseof the FF map, with the lowest values close to 15 nm NaF and with littledependence on GGI. Typical saturation current values close to the 15 nmNaF region are around 1E-6 A/cm² (total area, not active area) withseries resistance around 1.0 Ohm, and the ideality factor in the 1.50 to1.75 range. The high ideality factors might be due to lateralnon-uniformity [67].

The shunt resistance reaches its maximum in the GGI=0.36 and NaF=15 nmregion, with a clear dependence on both GGI and NaF. However forco-evaporated CIGSe, no influence of Na on the shunt resistance could beobserved [50]. The drop in ideality factor accompanied by an increase inshunt resistance due to optimized NaF conditions might be explained byimproved lateral uniformity, e.g. less impurity phases. SEM partiallysupports this, but more work is needed to separate lateral variationfrom variations in depth.

The highest PL intensities are found for the highest open-circuitvoltages, and this suggests a reduction in non-radiative recombinationnear the CIGS surface to be partially responsible for the improvedV_(OC). The bandgap E_(g) extracted from EQE (at 20% EQE) shows adependence on both GGI and NaF, with the highest E_(g) for 0 nm NaF andhigh GGI. This suggests an increase in GGI for the top layer for highGGI and 0 nm NaF. The decrease of GGI near the CIGSe surface for 10-20nm NaF is in agreement with the SIMS results (GGI=0.35).

To gain insight into the influence of both the GGI depth profile andCIGSe material quality on the V_(OC), a contour plot of E_(g)/q−V_(OC)is shown using E_(g) derived from EQE. The map clearly shows improvedmaterial quality with increasing NaF thickness. Even though GGIdefinitely influences V_(OC), the higher V_(OC) is obtained for thebetter material quality, not the higher E_(g) at the surface. The higherJ_(SC) for the higher NaF can be attributed to the combination of thelower E_(g) in the top layer and the higher material quality.

FIG. 18 shows the EQE spectrum and J-V curve, in addition to the J-Vparameters for the champion cell (active-area efficiency=16.0%). Thiscell is made with 15 nm NaF, CGI=0.85, GGI=0.39, and withoutanti-reflection coating. The dip in EQE slightly above 700 nm is anartifact of the EQE setup.

The location of the NaF deposition within the film stack is critical.CIGSe films grown with NaF deposited on the Mo back contact resulted inpeeling during CBD-CdS. The process window for NaF on top of Cu(In, Ga)was found to be much wider.

These results show that NaF addition on top of Cu(In, Ga) prior to H₂Sebatch selenization results in reduced gallium content and an increase ingrain size for the top portion of the final CIGSe film. In addition,plan-view SEM imaging and device parameters (shunt resistance andideality factor) suggest an improvement in lateral uniformity (lessimpurity phases) for optimized NaF thickness. This suggests that theCIGSe film formation for the H₂Se batch selenization most likely startswith the formation of a top layer of Ga-poor CISe, followed by thein-diffusion of gallium from a Cu- and Ga-rich bottom layer [59, 69].

The CIGSe film had only a slight preferred (112) crystal orientationwith no clear effect of NaF. This suggests that NaF addition provideslimited control over the orientation of the starting Ga-poor CISecrystallites. Excessive air sensitivity and phase segregation of sodiumselenide and sodium oxide species throughout the CIGSe film might startlimiting the beneficial effects of Na [12, 17, 37, 44, 45].

It should be noted that the negative effects of Na, as proposed byHergert et al. [51] are mainly for solid-state reactions. The typicalbeneficial effect of Cu—Se is attributed to liquid-assisted growth [57,70], with the prerequisite that Cu—Se phases should not be fullyconsumed prior to their melting point (ranging from 377° C. to 523° C.for phases more Se-rich than Cu_(2−x)Se). Therefore, the beneficialeffect of Na might be the result of additional control over theliquid-assisted growth. Sodium selenides more Se-rich than Na₂Se areliquid starting at 258° C., and as such, might allow a wider temperaturewindow for the beneficial liquid-assisted growth. The wider growthwindow may help to organize the point defects during growth, therebyproviding an improved crystal structure.

CONCLUSIONS

These examples discuss a sodium fluoride (NaF) thickness variation studyfor the H₂Se batch furnace selenization of sputtered Cu(In,Ga) films ina wide range of Cu(In, Ga) film compositions to form CIGSe films andsolar cells. These results show that NaF addition on top of Cu(In, Ga)prior to H₂Se batch selenization results in reduced gallium content andan increase in grain size for the top region of the final CIGSe film. Inaddition, plan-view SEM imaging and device parameters suggest animprovement in lateral uniformity for optimized NaF thickness.

The CIGSe film had only a slight preferred (112) crystal orientationwith no clear effect of NaF. The addition of NaF resulted in improvementin all relevant device parameters: efficiency, open-circuit voltage,short-circuit current, and fill factor. Furthermore, an increase in thenet hole concentration and a reduction in non-radiative recombination isobserved. Further analysis showed that saturation current, idealityfactor, series resistance, and shunt resistance all improve foroptimized NaF conditions.

These results, combined with the various mechanisms proposed by previousauthors, suggests that the negative effects of Na on H₂Se batch furnaceselenization of sputtered Cu(In, Ga) films, being the GGI inhomogeneity,might be mainly due to solid-state reactions, whereas the positiveeffects of Na, being the increase in net hole concentration and thereduction in non-radiative recombination, might be mainly dictated byliquid-assisted growth.

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Although the foregoing examples have been described in some detail forpurposes of clarity of understanding, the invention is not limited tothe details provided. There are many alternative ways of implementingthe invention. The disclosed examples are illustrative and notrestrictive.

What is claimed:
 1. A method for forming a material on a substrate, themethod comprising: forming a metal film on the substrate; after theforming, inserting the substrate into a processing system; after theinserting, heating the substrate to a temperature between 100C and 700C;after the heating to a temperature, depositing a Na-containing layer onthe metal film; and after the depositing, providing a chalcogen.
 2. Themethod of claim 1 wherein the Na-containing layer is NaF deposited byChemical Vapor Deposition (CVD).
 3. The method of claim 2 wherein theNaF layer is deposited using a CVD precursor comprising one of sodiumhexafluoro-iso-propoxide, sodium perfluoro-t-butoxide, sodiumhexafluoroacetylacetonate, or sodium heptafluoro-octadionate.
 4. Themethod of claim 1 wherein a thickness of the Na-containing layer isbetween 5 nm and 100 nm.
 5. The method of claim 1 further comprisingannealing the substrate after the providing a chalcogen step.
 6. Themethod of claim 1 wherein the processing system is a batch processingsystem.
 7. The method of claim 1 wherein the processing system is anin-line processing system.
 8. The method of claim 1 wherein theprocessing system is a rapid thermal processing system.
 9. The method ofclaim 1 wherein the metal film comprises Cu, In, and Ga.
 10. The methodof claim 9 wherein the metal film further comprises Ag.
 11. A method forforming a material on a substrate, the method comprising: forming ametal film on the substrate; after the forming, inserting the substrateinto a processing system; after the inserting, heating the substrate toa temperature between 100C and 700C; after the heating to a temperature,providing a Na-containing Chemical Vapor Deposition (CVD) precursor anda chalcogen.
 12. The method of claim 11 wherein the Na-containing CVDprecursor comprises one of sodium hexafluoro-iso-propoxide, sodiumperfluoro-t-butoxide, sodium hexafluoroacetylacetonate, or sodiumheptafluoro-octadionate.
 13. The method of claim 11 further comprisingannealing the substrate after the providing a Na-containing CVDprecursor and a chalcogen step.
 14. The method of claim 11 wherein theprocessing system is a batch processing system.
 15. The method of claim11 wherein the processing system is an in-line processing system. 16.The method of claim 11 wherein the processing system is a rapid thermalprocessing system.
 17. The method of claim 11 wherein the metal filmcomprises Cu, In, and Ga.
 18. The method of claim 17 wherein the metalfilm further comprises Ag.